[PATCH V7 02/17] SPEAr13xx: Add PCIe host controller base driver support.

[arnd@arndb.de (Arnd Bergmann)]

On Monday 11 April 2011, pratyush wrote:
> On 3/23/2011 1:58 PM, Arnd Bergmann wrote:
> > On Wednesday 23 March 2011, Viresh Kumar wrote:
> > 
> > The way I would recommend is to reserve a part of the system's virtual
> > address space for all I/O windows, and using iotable_init() to map
> > them contiguously. The first port will then be the only one that
> > can hold ISA ranges (needed for legacy VGA mode, for instance).
> > 
> 
> Sorry, may be I could not get this point correctly. Do you mean that,
> I should create a static mapping for IN0_MEM_SIZE (200 MB) and 
> IN_IO_SIZE (20 MB) during board initialization itself?

Only IN_IO_SIZE. The I/O space is implicitly assumed to be mapped, while
the memory space is mapped by device drivers individually.

> >> diff --git a/arch/arm/mach-spear13xx/include/mach/hardware.h b/arch/arm/mach-spear13xx/include/mach/hardware.h
> >> index fd8c2dc..6169d4f 100644
> >> --- a/arch/arm/mach-spear13xx/include/mach/hardware.h
> >> +++ b/arch/arm/mach-spear13xx/include/mach/hardware.h
> >> @@ -28,4 +28,8 @@
> >>  /* typesafe io address */
> >>  #define __io_address(n)		__io(IO_ADDRESS(n))
> > 
> > Please reread my previous comments. You have to redefine __io() in order to make
> > the I/O port accesses work. When you do that, you cannot define
> > __io_address (which is used by non-PCI code) as using __io.
> > 
> 
> __io_address is not used by PICe routines. Also, this is not part of 
> this patch. 

Yes, that was my point.

> >> +/*
> >> + * In current implementation address translation is done using IN0 only. So IN1
> >> + * start address and IN0 end address has been kept same
> >> +*/
> >> +#define IN1_MEM_SIZE	(0 * 1024 * 1024 - 1)
> >> +#define IN_IO_SIZE	(20 * 1024 * 1024 - 1)
> >> +#define IN_CFG0_SIZE	(1 * 1024 * 1024 - 1)
> >> +#define IN_CFG1_SIZE	(1 * 1024 * 1024 - 1)
> >> +#define IN_MSG_SIZE	(1 * 1024 * 1024 - 1)
> > 
> > Is IN_IO_SIZE per host, or this shared across all hosts?
> 
> This is per host. So is it not a practical size?
> What should be a reasonable IO size?

64 KB is more than enough per host. That is the maximum that an x86 PC
can address, so devices usually use very little of this, if anything.

There are some advantages to using 64KB combined for all hosts, but
the easiest way should probably be to reserve 1 MB for the space
and use 64 KB for each of them.

If you have a PCI-ISA bridge chip or a card that has one, it needs to
be on a host that has its I/O space in the first 64 KB.

	Arnd