[PATCH V2 1/4] amd iommu: shift p2m type bits from bit 9 to bit 12 in p2m flags

[Wei Wang2 <wei.wang2@amd.com>]

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--
Advanced Micro Devices GmbH
Sitz: Dornach, Gemeinde Aschheim, 
Landkreis München Registergericht München, 
HRB Nr. 43632
WEEE-Reg-Nr: DE 12919551
Geschäftsführer:
Alberto Bozzo, Andrew Bowd

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# HG changeset patch
# User Wei Wang <wei.wang2@amd.com>
# Node ID 848156536fda60540fe3f482a1fc1d34eeb3532d
# Parent  3f00c5faa12aed4d0993391f71b7f12cf92f0208
AMD IOMMU hardware uses bit 9 - bit 11 to encode lower page levels. p2m type bits in p2m flags has to be shifted from bit 9 to bit 12.  Also, bit 52 to bit 60 cannot be non-zero for iommu pde. So, the definition of p2m_ram_rw has to be swapped with p2m_invalid. 

Signed-off-by: Wei Wang <wei.wang2@amd.com>

diff -r 3f00c5faa12a -r 848156536fda xen/arch/x86/mm/p2m.c
--- a/xen/arch/x86/mm/p2m.c	Wed Apr 13 16:10:26 2011 +0100
+++ b/xen/arch/x86/mm/p2m.c	Fri Apr 15 13:51:54 2011 +0200
@@ -80,7 +80,12 @@ unsigned long p2m_type_to_flags(p2m_type
 {
     unsigned long flags;
 #ifdef __x86_64__
-    flags = (unsigned long)(t & 0x3fff) << 9;
+    /*
+     * AMD IOMMU: When we share p2m table with iommu, bit 9 - bit 11 will be
+     * used for iommu hardware to encode next io page level. Bit 59 - bit 62
+     * are used for iommu flags, We could not use these bits to store p2m types.
+     */
+    flags = (unsigned long)(t & 0x7f) << 12;
 #else
     flags = (t & 0x7UL) << 9;
 #endif
@@ -1826,6 +1831,9 @@ static mfn_t p2m_gfn_to_mfn_current(stru
             p2mt = p2m_flags_to_type(l1e_get_flags(l1e));
             ASSERT(l1e_get_pfn(l1e) != INVALID_MFN || !p2m_is_ram(p2mt));
 
+            if ( l1e.l1 == 0 )
+                p2mt = p2m_invalid;
+
             if ( p2m_flags_to_type(l1e_get_flags(l1e))
                  == p2m_populate_on_demand )
             {
diff -r 3f00c5faa12a -r 848156536fda xen/include/asm-x86/p2m.h
--- a/xen/include/asm-x86/p2m.h	Wed Apr 13 16:10:26 2011 +0100
+++ b/xen/include/asm-x86/p2m.h	Fri Apr 15 13:51:54 2011 +0200
@@ -63,9 +63,15 @@
  * Further expansions of the type system will only be supported on
  * 64-bit Xen.
  */
+
+/*
+ * AMD IOMMU: When we share p2m table with iommu, bit 52 -bit 58 in pte 
+ * cannot be non-zero, otherwise, hardware generates io page faults when 
+ * device access those pages. Therefore, p2m_ram_rw has to be defined as 0.
+ */
 typedef enum {
-    p2m_invalid = 0,            /* Nothing mapped here */
-    p2m_ram_rw = 1,             /* Normal read/write guest RAM */
+    p2m_ram_rw = 0,             /* Normal read/write guest RAM */
+    p2m_invalid = 1,            /* Nothing mapped here */
     p2m_ram_logdirty = 2,       /* Temporarily read-only for log-dirty */
     p2m_ram_ro = 3,             /* Read-only; writes are silently dropped */
     p2m_mmio_dm = 4,            /* Reads and write go to the device model */
@@ -375,7 +381,13 @@ static inline p2m_type_t p2m_flags_to_ty
 {
     /* Type is stored in the "available" bits */
 #ifdef __x86_64__
-    return (flags >> 9) & 0x3fff;
+    /*
+     * AMD IOMMU: When we share p2m table with iommu, bit 9 - bit 11 will be
+     * used for iommu hardware to encode next io page level. Bit 59 - bit 62
+     * are used for iommu flags, We could not use these bits to store p2m types.
+     */
+
+    return (flags >> 12) & 0x7f;
 #else
     return (flags >> 9) & 0x7;
 #endif

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