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From: Brad Hards <bradh@frogmouth.net>
Date: Sat, 16 Apr 2011 16:33:02 +1000
References: <BANLkTik3hmvH6_tUuEZjR8j0L04PdCk7mw@mail.gmail.com>
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Subject: Re: [Qemu-devel] Bug #757654: UHCI fails to signal stall response
	patch
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To: qemu-devel@nongnu.org
Cc: Jan Vesely <jano.vesely@gmail.com>

On Sat, 16 Apr 2011 06:57:00 am Jan Vesely wrote:
> +        s->status |= UHCI_STS_USBERR;
This is per UHCI 1.1D Section 4.1.5. Looks good.

> +        *int_mask |= 0x02;
> +        if (td->ctrl & TD_CTRL_IOC)
> +            *int_mask |= 0x01;
> +        uhci_update_irq(s);
I see "A hardware interrupt is signalled to the system", but can you provide a 
little explanation of why this particular interrupt mask?

> +        s->status |= UHCI_STS_USBERR;
This is per UHCI 1.1d Section 4.1.4. Looks good.

> +        *int_mask |= 0x02;
> +        if (td->ctrl & TD_CTRL_IOC)
> +           *int_mask |= 0x01;
> +        uhci_update_irq(s);
I see "A hardware interrupt is signalled to the system", but can you provide a 
little explanation of why this particular interrupt mask?