From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:35217) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QEUJr-0003w1-El for qemu-devel@nongnu.org; Mon, 25 Apr 2011 18:31:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QEUJq-0008Ap-HT for qemu-devel@nongnu.org; Mon, 25 Apr 2011 18:31:51 -0400 Received: from hall.aurel32.net ([88.191.126.93]:49019) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QEUJq-0008Ag-Bg for qemu-devel@nongnu.org; Mon, 25 Apr 2011 18:31:50 -0400 Date: Tue, 26 Apr 2011 00:31:46 +0200 From: Aurelien Jarno Message-ID: <20110425223146.GG6181@volta.aurel32.net> References: <1303401708-5419-1-git-send-email-peter.maydell@linaro.org> <20110425210953.GH21831@volta.aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Subject: Re: [Qemu-devel] [PATCH] target-arm: Minimal implementation of performance counters List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Paul Brook , qemu-devel@nongnu.org, patches@linaro.org On Mon, Apr 25, 2011 at 10:59:52PM +0100, Peter Maydell wrote: > On 25 April 2011 22:09, Aurelien Jarno wrote: > > On Thu, Apr 21, 2011 at 05:01:48PM +0100, Peter Maydell wrote: > > >> +                tb_flush(env); > > > > If you flush all tbs, you also have to ensure that on the translate.c > > side, this is the last instruction of the tb. Otherwise, the rest of the > > TB will be executed with the wrong access rights. > > This is OK, because we can't get here unless we're in privileged > mode (PMUSERENR is never writable in user mode), and changing > PMUSERENR doesn't affect the access rights for privileged mode. > And a switch into user mode will be a change of TB anyway. > > (Compare the handling of the TEECR, which also doesn't need to change > TB after a tb_flush(), for the same reasons.) Ok, fine then. > > Instead of having this complex test for all cp15 access, but only for > > catching a few access to performance registers, wouldn't it make more > > sense to have this test and an exception triggering directly in > > helper.c? > > That was what my first design did, but in discussions on IRC > with Paul Brook he basically said that you can't generate an > exception in the helper routine, you have to either generate > runtime code to do the test or throw away the TBs. Unfortunately > I forget the exact rationale, so I've cc'd Paul to remind me :-) This is something strange, plenty of targets are raising exceptions from helpers without any problem. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net