From mboxrd@z Thu Jan  1 00:00:00 1970
From: Mark Brown <broonie@opensource.wolfsonmicro.com>
Subject: Re: [PATCH 1/2 v2] ASoC: soc-cache: block based rbtree
 compression
Date: Tue, 3 May 2011 16:55:59 +0100
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To: Takashi Iwai <tiwai@suse.de>
Cc: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>, alsa-devel@alsa-project.org, patches@opensource.wolfsonmicro.com, Liam Girdwood <lrg@ti.com>, Liam Girdwood <lrg@slimlogic.co.uk>
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On Tue, May 03, 2011 at 05:54:21PM +0200, Takashi Iwai wrote:
> Mark Brown wrote:

> > We'll want to do that as well, but we still want the actual data
> > structure underneath to support that.  Since most register maps that
> > benefit from compression are also sparse rbtree is the common case for
> > getting a win from this.

> Hm, but iteration in the sorted order is pretty easy and cheap in
> rb-tree structure.  It's not necessarily to be exported in an array.

I2C and SPI controllers don't typically do gather terribly well, though,
and there is a win from reducing the number of rbtree nodes anyway.