[U-Boot] [PATCH] ARM: i.MX51: Config option to disable PLL1

[David Jander <david.jander@protonic.nl>]

On Fri, 27 May 2011 12:13:32 +0200
Stefano Babic <sbabic@denx.de> wrote:

> On 05/26/2011 07:00 PM, David Jander wrote:
> > i.MX51 PLL1 seems to have stability problems. It is advised to not use it,
> > although it is unclear whether all boards and/or chip revisions have this
> > problem. Using PLL2 for the core and DDR2 seems to fix the problem.
> > No official errata yet.
> > 
> 
> Hi David,
> 
> do you get some info from Freescale's FAE ?

Yes.

> Is this issue strictly
> related to the processor or can be board related ?

AFAIK, this issue could also be board-related. In other words, if one designs
a board that powers vpll* from a higher voltage than nominal mentioned
in the datasheet, chances could be lower.

> I hope someone from Freescale can help us to understand this issue.

I think I already know quite a lot about it (feel free to ask me off-list).

> > Signed-off-by: David Jander <david@protonic.nl>
> > ---
> >  arch/arm/cpu/armv7/mx5/lowlevel_init.S |   16 ++++++++++++++++
> >  1 files changed, 16 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
> > b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 96ebfe2..e1d6c35 100644
> > --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
> > +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
> > @@ -153,7 +153,11 @@
> >  	mov r1, #0x4
> >  	str r1, [r0, #CLKCTL_CCSR]
> >  
> > +#if defined(CONFIG_MX51_AVOID_PLL1)
> 
> If you add a new CONFIG_, you must document it in the README file.

Ah, ok, thanks for pointing out.

> Rather I cannot get a better feedback, I do not know this issue on the
> i.MX51. As you reported, it seems still unclear what happens.

Symptoms are sudden complete freeze of the ARM core, and either stable or
unstable image corruption on the LCD.

Best regards,

-- 
David Jander
Protonic Holland.