From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ankita Garg Date: Mon, 30 May 2011 12:09:40 +0530 Subject: [U-Boot] Help with exporting memory power management info in u-boot Message-ID: <20110530063940.GB16331@in.ibm.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi, Memory hardware today offers capabilities for managing power consumption, like multiple lower power statest. Few SoCs, like the TI Panda board, offers support for Partial Array Self Refresh (PASR), by which partial areas of memory could be turned off to save power. Further, few other SoCs have multiple memory controllers, like Samsung Exynos 4210, where each controller independently transitions memory under it into lower power states depending on certain criteria. Each of these capabilities are supported by the hardware at a particular granularity. For example, PASR could be supported at the level of a memory bank, i.e, a bank of memory that is free could be turned off, independent of the other banks. Inorder to exploit these features, the Linux VM subsystem needs to be modified to take into account the physical memory topology when managing memory. We proposed a generic memory regions infrastructure, that could be used to tag boundaries of memory blocks which belong to a specific memory power management domain and further enable exploitation of platform capabilities. The details of this framework can be found here: https://lkml.org/lkml/2011/5/27/177 Memory region is a layer of abstraction that would be created at boot time, with information from firmware regarding the granularity at which memory power can be managed on the platform. We would like to work towards having this information exported by u-boot. A sample interface we are looking at is a device tree node that would provide the number, size and starting address corresponding to the memory power domains on the underlying platform. In this regard, we want some help from the u-boot community on designing the interfaces. Further, we would like to collaborate with all the SoCs that have support for managing memory power on their boards, so we could design a generic interface that can be exploited by all. -- Regards, Ankita Garg (ankita at in.ibm.com) Linux Technology Center IBM India Systems & Technology Labs, Bangalore, India