From: dave.martin@linaro.org (Dave Martin)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 07/11] ARM: proc: add proc info for Cortex-A15MP using classic page tables
Date: Tue, 7 Jun 2011 17:18:27 +0100 [thread overview]
Message-ID: <20110607161827.GC19855@arm.com> (raw)
In-Reply-To: <1307379355-13802-8-git-send-email-will.deacon@arm.com>
On Mon, Jun 06, 2011 at 05:55:51PM +0100, Will Deacon wrote:
> Multicore implementations of the Cortex-A15 require bit 6 of the
> auxiliary control register to be set in order for cache and TLB
> maintenance operations to be broadcast between CPUs.
>
> This patch adds a new proc_info structure for Cortex-A15, which enables
> the SMP bit during setup and includes the new HWCAPs for integer
> division and VFPv4.
>
> Signed-off-by: Will Deacon <will.deacon@arm.com>
> ---
> arch/arm/mm/proc-v7.S | 20 ++++++++++++++++++--
> 1 files changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> index 8eba506..1e74e16 100644
> --- a/arch/arm/mm/proc-v7.S
> +++ b/arch/arm/mm/proc-v7.S
> @@ -275,12 +275,18 @@ cpu_resume_l1_flags:
> */
> __v7_ca5mp_setup:
> __v7_ca9mp_setup:
> + mov r10, #(1 << 0) @ TLB ops broadcasting
> + b 1f
> +__v7_ca15mp_setup:
> + mov r10, #0
> +1:
> #ifdef CONFIG_SMP
> ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
> ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
> tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
> - orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and
> - mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting
> + orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
> + orreq r0, r0, r10 @ Enable CPU-specific SMP bits
> + mcreq p15, 0, r0, c1, c0, 1
> #endif
> __v7_setup:
> adr r12, __v7_setup_stack @ the local stack
> @@ -480,6 +486,16 @@ __v7_ca9mp_proc_info:
> .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
>
> /*
> + * ARM Ltd. Cortex A15 processor.
> + */
> + .type __v7_ca15mp_proc_info, #object
> +__v7_ca15mp_proc_info:
> + .long 0x410fc0f0
> + .long 0xff0ffff0
> + __v7_proc __v7_ca15mp_setup, HWCAP_VFPv4 | HWCAP_IDIV
As for A5, do we need to include additional VFP hwcap flags?
---Dave
next prev parent reply other threads:[~2011-06-07 16:18 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-06-06 16:55 [PATCH 00/11] Core support for Cortex-A5 and Cortex-A15 Will Deacon
2011-06-06 16:55 ` [PATCH 01/11] arm: Convert v7 proc infos into a common macro Will Deacon
2011-06-06 16:55 ` [PATCH 02/11] arm: Add Cortex A5 proc info Will Deacon
2011-06-06 16:55 ` [PATCH 03/11] ARM: hwcaps: use shifts instead of hardcoded constants Will Deacon
2011-06-06 16:55 ` [PATCH 04/11] ARM: hwcaps: add new HWCAP defines for ARMv7-A Will Deacon
2011-06-06 16:55 ` [PATCH 05/11] ARM: proc: reorder macro parameters for __v7_proc macro Will Deacon
2011-06-06 16:55 ` [PATCH 06/11] ARM: cortex-a5: add HWCAP_VFPv4D16 to proc info structure Will Deacon
2011-06-07 16:17 ` Dave Martin
2011-06-07 16:22 ` Will Deacon
2011-06-08 9:05 ` Dave Martin
2011-06-08 9:24 ` Will Deacon
2011-06-06 16:55 ` [PATCH 07/11] ARM: proc: add proc info for Cortex-A15MP using classic page tables Will Deacon
2011-06-07 16:18 ` Dave Martin [this message]
2011-06-06 16:55 ` [PATCH 08/11] ARM: perf: remove confusing comment from v7 perf events backend Will Deacon
2011-06-06 16:55 ` [PATCH 09/11] ARM: perf: add PMUv2 common event definitions Will Deacon
2011-06-07 7:18 ` Jean Pihet
2011-06-07 8:51 ` Will Deacon
2011-06-06 16:55 ` [PATCH 10/11] ARM: perf: add support for the Cortex-A5 PMU Will Deacon
2011-06-06 16:55 ` [PATCH 11/11] ARM: perf: add support for the Cortex-A15 PMU Will Deacon
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