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Date:   Mon, 13 Jun 2011 20:34:03 -0700
From:   Guenter Roeck <guenter.roeck@ericsson.com>
To:     David Daney <ddaney@caviumnetworks.com>
CC:     "linux-mips@linux-mips.org" <linux-mips@linux-mips.org>
Subject: Re: Linux 2.6.39 on Cavium CN38xx
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On Mon, Jun 13, 2011 at 05:51:11PM -0400, Guenter Roeck wrote:
[ ... ]
> > >
> > > The actual interrupt causing trouble and spurious interrupts in my case is,
> > > oddly enough, STATUSF_IP0. So far I have been unable to track down how that
> > > is triggered; I don't see the bit being set set in C0_CAUSE anywhere.
> > >
> > > Are there any means to trigger an IP0 interrupt other than by writing STATUSF_IP0
> > > into the C0_CAUSE register ?
> > >
> > 
> > No.  Nothing that I know of ever uses IP0 and IP1, so they should always 
> > be cleared.
> > 
> Exactly what I figured, yet I still get those spurious interrupts if IP0 is enabled.
> Something odd is definitely going on in my system.
> 
> Besides the above, my hopefully final problem is that timer interrupts are only
> received by CPU 0. Any idea what to look for to fix this problem ?
> 
Found the problem. Apparently the BIOS resets CvmCtl[IPTI] to 0. This causes both
the spurious interrupt on IP0 without setting C0_CAUSE, and the (perceived)
lack of timer interrupts. In other words, it _is_ possible to trigger IP0 interrupts
without setting STATUSF_IP0 in C0_CAUSE ... the interrupt will happen, but C0_CAUSE
will not be set.

Interesting learning experience...

Thanks,
Guenter