diff for duplicates of <201107061544.20859.arnd@arndb.de> diff --git a/a/1.txt b/N1/1.txt index 3c2b81e..8e49462 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -8,12 +8,12 @@ On Wednesday 06 July 2011, Barry Song wrote: > > > > sys-iobg { > > ranges = <0 0x48000000 0x40000>; -> > clock-controller at 0x88000000 { +> > clock-controller@0x88000000 { > > compatible = "sirf,prima2-clkc"; > > reg = <0 0x1000>; > > } > > -> > reset-controller at 0x88010000 { +> > reset-controller@0x88010000 { > > compatible = "sirf,prima2-rstc"; > > reg = <0x10000 0x1000>; > > }; @@ -48,7 +48,7 @@ To stay in the example, this would mean doing something like 3 0 0x90010000 0x07fe0000 // disp-iobg ... >; - l2-cache-controller at 80040000 { + l2-cache-controller@80040000 { compatible = "arm,pl310-cache"; reg = <0 0x40000 0x1000>; interrupts = <59>; @@ -58,12 +58,12 @@ To stay in the example, this would mean doing something like #address-cells = <1>; #size-cells = <1>; ranges = <1 0 0 0x40000>; - clock-controller at 88000000 { + clock-controller@88000000 { compatible = "sirf,prima2-clkc"; reg = <0 0x1000>; } - reset-controller at 88010000 { + reset-controller@88010000 { compatible = "sirf,prima2-rstc"; reg = <0x10000 0x1000>; }; @@ -79,7 +79,7 @@ To stay in the example, this would mean doing something like > >> + #size-cells = <1>; > >> + ranges = <0x98000000 0x98000000 0x8000000>; > >> + -> >> + graphics at 0x98000000 { +> >> + graphics@0x98000000 { > >> + compatible = "sirf,prima2-graphics"; > >> + reg = <0x98000000 0x8000000>; > >> + interrupts = <6>; @@ -103,7 +103,7 @@ that makes it possible that this is the version that csr has modified. > >> + #size-cells = <1>; > >> + ranges = <0xa0000000 0xa0000000 0x8000000>; > >> + -> >> + multimedia at 0xa0000000 { +> >> + multimedia@0xa0000000 { > >> + compatible = "sirf,prima2-multimedia"; > >> + reg = <0xa0000000 0x8000000>; > >> + interrupts = <5>; diff --git a/a/content_digest b/N1/content_digest index 4201ee2..0203a85 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,10 +1,24 @@ "ref\01309945678-18813-1-git-send-email-bs14@csr.com\0" "ref\0201107061341.38591.arnd@arndb.de\0" "ref\0CAGsJ_4zzrsKZRR4KCaeFGL9iT5OfMdhKjJE1wG3CGh8M2U4-UQ@mail.gmail.com\0" - "From\0arnd@arndb.de (Arnd Bergmann)\0" - "Subject\0[PATCH 1/3] ARM: CSR: Adding CSR SiRFprimaII board support\0" + "ref\0CAGsJ_4zzrsKZRR4KCaeFGL9iT5OfMdhKjJE1wG3CGh8M2U4-UQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org\0" + "From\0Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>\0" + "Subject\0Re: [PATCH 1/3] ARM: CSR: Adding CSR SiRFprimaII board support\0" "Date\0Wed, 6 Jul 2011 15:44:20 +0200\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Barry Song <21cnbao-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" + "Cc\0linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org" + Barry Song <bs14-kQvG35nSl+M@public.gmane.org> + Bin Shi <Bin.Shi-kQvG35nSl+M@public.gmane.org> + devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org + workgroup.linux-kQvG35nSl+M@public.gmane.org + Zhiwu Song <Zhiwu.Song-kQvG35nSl+M@public.gmane.org> + Rongjun Ying <Rongjun.Ying-kQvG35nSl+M@public.gmane.org> + Binghua Duan <binghua.duan-kQvG35nSl+M@public.gmane.org> + Barry Song <Baohua.Song-kQvG35nSl+M@public.gmane.org> + tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org + Yuping Luo <Yuping.Luo-kQvG35nSl+M@public.gmane.org> + Huayi Li <Huayi.Li-kQvG35nSl+M@public.gmane.org> + " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" "\00:1\0" "b\0" "On Wednesday 06 July 2011, Barry Song wrote:\n" @@ -17,12 +31,12 @@ "> >\n" "> > sys-iobg {\n" "> > ranges = <0 0x48000000 0x40000>;\n" - "> > clock-controller at 0x88000000 {\n" + "> > clock-controller@0x88000000 {\n" "> > compatible = \"sirf,prima2-clkc\";\n" "> > reg = <0 0x1000>;\n" "> > }\n" "> >\n" - "> > reset-controller at 0x88010000 {\n" + "> > reset-controller@0x88010000 {\n" "> > compatible = \"sirf,prima2-rstc\";\n" "> > reg = <0x10000 0x1000>;\n" "> > };\n" @@ -57,7 +71,7 @@ "\t\t\t 3 0 0x90010000 0x07fe0000 // disp-iobg\n" " ... >;\n" "\n" - " l2-cache-controller at 80040000 {\n" + " l2-cache-controller@80040000 {\n" " compatible = \"arm,pl310-cache\";\n" " reg = <0 0x40000 0x1000>;\n" " interrupts = <59>;\n" @@ -67,12 +81,12 @@ "\t\t\t#address-cells = <1>;\n" " \t #size-cells = <1>;\n" " ranges = <1 0 0 0x40000>;\n" - " clock-controller at 88000000 {\n" + " clock-controller@88000000 {\n" " compatible = \"sirf,prima2-clkc\";\n" " reg = <0 0x1000>;\n" " }\n" "\n" - " reset-controller at 88010000 {\n" + " reset-controller@88010000 {\n" " compatible = \"sirf,prima2-rstc\";\n" " reg = <0x10000 0x1000>;\n" " };\n" @@ -88,7 +102,7 @@ "> >> + #size-cells = <1>;\n" "> >> + ranges = <0x98000000 0x98000000 0x8000000>;\n" "> >> +\n" - "> >> + graphics at 0x98000000 {\n" + "> >> + graphics@0x98000000 {\n" "> >> + compatible = \"sirf,prima2-graphics\";\n" "> >> + reg = <0x98000000 0x8000000>;\n" "> >> + interrupts = <6>;\n" @@ -112,7 +126,7 @@ "> >> + #size-cells = <1>;\n" "> >> + ranges = <0xa0000000 0xa0000000 0x8000000>;\n" "> >> +\n" - "> >> + multimedia at 0xa0000000 {\n" + "> >> + multimedia@0xa0000000 {\n" "> >> + compatible = \"sirf,prima2-multimedia\";\n" "> >> + reg = <0xa0000000 0x8000000>;\n" "> >> + interrupts = <5>;\n" @@ -151,4 +165,4 @@ "\n" "\tArnd" -bdf9d202bfb38309f5f2d97a6698ebc50042eb82c1c336a73c14d35605877f27 +1061c89414ba18e4aad64780a6d0b780497144ba32884f9bfd1a3777b5f0aa29
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