From mboxrd@z Thu Jan 1 00:00:00 1970 From: Aleksey Shevkov Date: Mon, 11 Jul 2011 16:48:06 +0600 Subject: [ath9k-devel] AR9380 - Transmit power control per packet In-Reply-To: References: <001501cc3a22$f49d4b70$ddd7e250$@gmx.net> <000801cc3d50$d4373e50$7ca5baf0$@gmx.net> <20110708112722.GA7392@infinet.ru> <20110708141933.GA7759@infinet.ru> Message-ID: <20110711104806.GA1994@infinet.ru> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: ath9k-devel@lists.ath9k.org On Sat, Jul 09, 2011 at 08:21:20AM +0800, Adrian Chadd wrote: > On 8 July 2011 22:19, Alex Hacker wrote: > > Oh sorry, let me take last words back. Robert is right it does not work with AR9380. > > Power control mechanism does not depend on AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE bit. > > The AR_PHY_POWER_TX_RATE_MAX register contains a different value 0x00367044 on AR9380 and > > 0x0000007f on older chips. > > Except that the AR9300 TPC enable code does exactly the same as the > TPC enable code for the AR5416 series chips. > Shure exactly same code. I havn't any other source of information about AR9380 PHY except the ar9003_phy.h file. > By the way, the 11n rate scenario code doesn't have any per-rate TPC > code in it. Only the TX power for rate series 0 is set. Is this > potentially causing you problems? > I test it with single series NoAck packets (XmitDataTries0 = 1, XmitPower != 0). The AR9380 transmit at the power configured for self generated packets AR_PHY_POWER_TX_RATEn registers not at the power set in AR_XmitPower field of ctl11 word of TX descriptor. > From a cursory examination of the AR9300 code (and I should say, I've > not even used an AR9300 yet, let alone tinkered with the TPC stuff) it > looks all very straightforward. Unless some other chip functionality > is required that hasn't been ported to ath9k, it "should just work". > My primary distrust falls on the AR_PHY_POWER_TX_RATE_MAX register. Although the AR9380 chip has very different PHY, this register is defined at the same adress as in the older chips (I'm afraid the definition is copy-pasted from ar9002_phy.h file). This register holds the value prior to the last write, i.e. REG_WRITE(AR_PHY_POWER_TX_RATE_MAX,x) REG_WRITE(AR_PHY_POWER_TX_RATE_MAX,y) REG_READ(AR_PHY_POWER_TX_RATE_MAX) == x This is not look like ordinary PHY register. > Sorry, I can't be more helpful than that. > Thank you Adrian for you attention to this problem! I am ensured that all together we found the solution. > (Also, it'd be nice if someone contributed per-packet TPC support - > proper support at that! - to ath9k. :) > I think about it just some time later. Currently really very busy on my primary job. I found some other HW problems on AR9380 which does not allow me to finish MIMO 3x3 support for our equipment. > > adrian