From mboxrd@z Thu Jan  1 00:00:00 1970
From: Alex Hacker <hacker@epn.ru>
Date: Tue, 12 Jul 2011 13:03:55 +0600
Subject: [ath9k-devel] AR9380 - Transmit power control per packet
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References: <001501cc3a22$f49d4b70$ddd7e250$@gmx.net>
	<000801cc3d50$d4373e50$7ca5baf0$@gmx.net>
	<20110708112722.GA7392@infinet.ru>
	<20110708141933.GA7759@infinet.ru>
	<CAJ-VmomAH=A1WS6Of29Po=nUNObHVrzAa5RMbbLmpxVjw2tsXQ@mail.gmail.com>
	<20110711104806.GA1994@infinet.ru>
	<CAJ-Vmo=WuCVdSEAoB+wQbM2PJDrbpGn+SeKZX6SsJXZx+i9Q8A@mail.gmail.com>
	<20110711151328.GA2696@infinet.ru>
	<CAD2nsn1AgTZVVF7W5-iVFOT6nF-w0RFxkvNRJzhnQjyU5Pr6Og@mail.gmail.com>
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To: ath9k-devel@lists.ath9k.org

I found the cause of TPC malfunction. As I assumed early, usage of
AR_PHY_POWER_TX_RATE_MAX register in AR9380 is incorrect. The following
lines should be removed from ar9003_phy.h file.
These registers does not exists:

--- ar9003_phy.h.orig	2011-03-30 16:25:00.000000000 +0600
+++ ar9003_phy.h	2011-07-12 12:53:30.000000000 +0600
@@ -733,9 +733,6 @@
 #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN  0x0000000e
 #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN_S 1
 
-#define AR_PHY_POWER_TX_RATE1   0x9934
-#define AR_PHY_POWER_TX_RATE2   0x9938
-#define AR_PHY_POWER_TX_RATE_MAX    0x993c
 #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
 #define PHY_AGC_CLR             0x10000000
 #define RFSILENT_BB             0x00002000

The AR_PHY_PWRTX_MAX register should be used instead. This register currently
do not hold MAX_RATE_POWER value, but 6th bit controls the TPC enable.
Now all works as expected for AR9380.

Best regards,
Alex.