[U-Boot] i.MX51: FEC: Cache coherency problem?

[David Jander <david.jander@protonic.nl>]

Hi all,

I am busy debugging a problem with the i.MX51 FEC ethernet driver, that
stopped working after upgrading u-boot. Before the upgrade I used
v2010.06-rc3, which worked fine.
I gave up on trying to find the difference beween the old version and this one
that broke it.... due to BSP issues, git bisecting seems a monumental task I
am not considering yet.
The funny part is that it seems to work fine if I disable data-caches!
With data caches enabled, it hangs in the following while loop in fec_send(),
at line 592:

...
584         /*
585          * Enable SmartDMA transmit task
586          */
587         fec_tx_task_enable(fec);
588 
589         /*
590          * wait until frame is sent .
591          */
592         while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
593                 udelay(1);
594         }
...

If I change this code in the following way, the while loop exits successfully:

...
584         /*
585          * Enable SmartDMA transmit task
586          */
587         flush_cache(&fec->tbd_base[fec->tbd_index], 4);
588         fec_tx_task_enable(fec);
589         flash_dcache_all();
590 
591         /*
592          * wait until frame is sent .
593          */
594         while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
595                 udelay(1);
596         }
...

Notice the cache flush calls at line 587 and 589. With these, sending
succeeds. The driver still hangs in receiving afterwards, but at least this
part seems to work. If I remove either of the two added lines, it stops
working again.

What is going on here? Why did this work with caches enabled before??

Best regards,

-- 
David Jander
Protonic Holland.