From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Jander Date: Tue, 19 Jul 2011 13:17:44 +0200 Subject: [U-Boot] i.MX51: FEC: Cache coherency problem? In-Reply-To: <4E256588.4010301@arcor.de> References: <20110718171836.67bfe605@archvile> <4E245C5C.4030303@ti.com> <4E256588.4010301@arcor.de> Message-ID: <20110719131744.403a81e6@archvile> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Tue, 19 Jul 2011 13:07:52 +0200 Matthias Wei?er wrote: > Dear Aneesh > > Am 18.07.2011 18:16, schrieb Aneesh V: > > commit c2dd0d45540397704de9b13287417d21049d34c6 > > armv7: integrate cache maintenance support > > > > In this patch I added a call to dcache_enable() at the beginning of > > board_init_r() for ARM(i.e. as soon as relocation is over). As a result > > D-cache will be enabled for all ARM platforms now unless > > CONFIG_SYS_DCACHE_OFF is set. > > Is this really a good idea? This will break a couple of boards using > non-cache-aware drivers. And there are a couple of them in u-boot. I > think d-cache should be opt-in rather then opt-out as long as there are > any drivers which didn't handle cached memory regions correct. i-cache > is much less problematic and can be enabled by default. > > If d-cache will be enabled by default on ARM I think I have to send a > patch for one of my boards :-) Exactly the issue I am having now... the fact that I was unaware of this patch and generally don't have much experience with solving cache-related issues apparently, made me waste a lot of time debugging the fec_mxc.c driver while the driver itself wasn't really broken (at least not more than before). Now I finally know what's wrong and am working on a proposed fix to make this one driver cache-aware. Best regards, -- David Jander Protonic Holland.