diff for duplicates of <20110719234158.2779.15394.stgit@ponder> diff --git a/a/1.txt b/N1/1.txt index f648ad3..18e4ae3 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -4,7 +4,7 @@ a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. -Signed-off-by: Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org> +Signed-off-by: Grant Likely <grant.likely@secretlab.ca> --- Hi all, @@ -47,14 +47,14 @@ index 0000000..4c05334 + bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk0p2 rw rootwait"; + }; + -+ memory@0 { ++ memory at 0 { + reg = < 0x00000000 0x40000000 >; + }; + -+ i2c@7000c000 { ++ i2c at 7000c000 { + clock-frequency = <400000>; + -+ codec: wm8903@1a { ++ codec: wm8903 at 1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupts = < 347 >; @@ -67,15 +67,15 @@ index 0000000..4c05334 + }; + }; + -+ i2c@7000c400 { ++ i2c at 7000c400 { + clock-frequency = <400000>; + }; + -+ i2c@7000c500 { ++ i2c at 7000c500 { + clock-frequency = <400000>; + }; + -+ i2c@7000d000 { ++ i2c at 7000d000 { + clock-frequency = <400000>; + }; + @@ -88,17 +88,17 @@ index 0000000..4c05334 + ext-mic-en-gpios = <&gpio 185 0>; + }; + -+ serial@70006300 { ++ serial at 70006300 { + clock-frequency = < 216000000 >; + }; + -+ sdhci@c8000200 { ++ sdhci at c8000200 { + gpios = <&gpio 69 0>, /* cd, gpio PI5 */ + <&gpio 57 0>, /* wp, gpio PH1 */ + <&gpio 155 0>; /* power, gpio PT3 */ + }; + -+ sdhci@c8000600 { ++ sdhci at c8000600 { + gpios = <&gpio 58 0>, /* cd, gpio PH2 */ + <&gpio 59 0>, /* wp, gpio PH3 */ + <&gpio 70 0>; /* power, gpio PI6 */ @@ -128,11 +128,11 @@ index 0000000..1940cae + reg = < 0x00000000 0x40000000 >; + }; + -+ serial@70006300 { ++ serial at 70006300 { + clock-frequency = < 216000000 >; + }; + -+ sdhci@c8000400 { ++ sdhci at c8000400 { + gpios = <&gpio 69 0>, /* cd, gpio PI5 */ + <&gpio 57 0>, /* wp, gpio PH1 */ + <&gpio 70 0>; /* power, gpio PI6 */ @@ -157,7 +157,7 @@ index 0000000..18a1f45 + #size-cells = <1>; + ranges; + -+ intc: interrupt-controller@50041000 { ++ intc: interrupt-controller at 50041000 { + compatible = "nvidia,tegra20-gic", "arm,gic"; + interrupt-controller; + #interrupt-cells = <1>; @@ -167,7 +167,7 @@ index 0000000..18a1f45 + }; + + -+ i2c@7000c000 { ++ i2c at 7000c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; @@ -175,7 +175,7 @@ index 0000000..18a1f45 + interrupts = < 70 >; + }; + -+ i2c@7000c400 { ++ i2c at 7000c400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; @@ -183,7 +183,7 @@ index 0000000..18a1f45 + interrupts = < 116 >; + }; + -+ i2c@7000c500 { ++ i2c at 7000c500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; @@ -191,7 +191,7 @@ index 0000000..18a1f45 + interrupts = < 124 >; + }; + -+ i2c@7000d000 { ++ i2c at 7000d000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2c"; @@ -199,7 +199,7 @@ index 0000000..18a1f45 + interrupts = < 85 >; + }; + -+ i2s@70002800 { ++ i2s at 70002800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2s"; @@ -208,7 +208,7 @@ index 0000000..18a1f45 + dma-channel = < 2 >; + }; + -+ i2s@70002a00 { ++ i2s at 70002a00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-i2s"; @@ -217,14 +217,14 @@ index 0000000..18a1f45 + dma-channel = < 1 >; + }; + -+ das@70000c00 { ++ das at 70000c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra20-das"; + reg = <0x70000c00 0x80>; + }; + -+ gpio: gpio@6000d000 { ++ gpio: gpio at 6000d000 { + compatible = "nvidia,tegra20-gpio"; + reg = < 0x6000d000 0x1000 >; + interrupts = < 64 65 66 67 87 119 121 >; @@ -232,60 +232,60 @@ index 0000000..18a1f45 + gpio-controller; + }; + -+ serial@70006000 { ++ serial at 70006000 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = < 68 >; + }; + -+ serial@70006040 { ++ serial at 70006040 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = < 69 >; + }; + -+ serial@70006200 { ++ serial at 70006200 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006200 0x100>; + reg-shift = <2>; + interrupts = < 78 >; + }; + -+ serial@70006300 { ++ serial at 70006300 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006300 0x100>; + reg-shift = <2>; + interrupts = < 122 >; + }; + -+ serial@70006400 { ++ serial at 70006400 { + compatible = "nvidia,tegra20-uart"; + reg = <0x70006400 0x100>; + reg-shift = <2>; + interrupts = < 123 >; + }; + -+ sdhci@c8000000 { ++ sdhci at c8000000 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000000 0x200>; + interrupts = < 46 >; + }; + -+ sdhci@c8000200 { ++ sdhci at c8000200 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000200 0x200>; + interrupts = < 47 >; + }; + -+ sdhci@c8000400 { ++ sdhci at c8000400 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000400 0x200>; + interrupts = < 51 >; + }; + -+ sdhci@c8000600 { ++ sdhci at c8000600 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000600 0x200>; + interrupts = < 63 >; diff --git a/a/content_digest b/N1/content_digest index d911758..5b92fa1 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,15 +1,7 @@ - "From\0Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>\0" + "From\0grant.likely@secretlab.ca (Grant Likely)\0" "Subject\0[PATCH] arm/dt: tegra devicetree support\0" "Date\0Tue, 19 Jul 2011 17:43:17 -0600\0" - "To\0Erik Gilling <konkers-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org>" - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - Colin Cross <ccross-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org> - Olof Johansson <olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org> - " linux-arm-kernel@list\0" - "Cc\0Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>" - swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org - " Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Everything required to populate NVIDIA Tegra devices from the device\n" @@ -18,7 +10,7 @@ "but it will be refined in follow on patches to configure clocks and\n" "pin IO from the device tree also.\n" "\n" - "Signed-off-by: Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>\n" + "Signed-off-by: Grant Likely <grant.likely@secretlab.ca>\n" "---\n" "\n" "Hi all,\n" @@ -61,14 +53,14 @@ "+\t\tbootargs = \"vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk0p2 rw rootwait\";\n" "+\t};\n" "+\n" - "+\tmemory@0 {\n" + "+\tmemory at 0 {\n" "+\t\treg = < 0x00000000 0x40000000 >;\n" "+\t};\n" "+\n" - "+\ti2c@7000c000 {\n" + "+\ti2c at 7000c000 {\n" "+\t\tclock-frequency = <400000>;\n" "+\n" - "+\t\tcodec: wm8903@1a {\n" + "+\t\tcodec: wm8903 at 1a {\n" "+\t\t\tcompatible = \"wlf,wm8903\";\n" "+\t\t\treg = <0x1a>;\n" "+\t\t\tinterrupts = < 347 >;\n" @@ -81,15 +73,15 @@ "+\t\t};\n" "+\t};\n" "+\n" - "+\ti2c@7000c400 {\n" + "+\ti2c at 7000c400 {\n" "+\t\tclock-frequency = <400000>;\n" "+\t};\n" "+\n" - "+\ti2c@7000c500 {\n" + "+\ti2c at 7000c500 {\n" "+\t\tclock-frequency = <400000>;\n" "+\t};\n" "+\n" - "+\ti2c@7000d000 {\n" + "+\ti2c at 7000d000 {\n" "+\t\tclock-frequency = <400000>;\n" "+\t};\n" "+\n" @@ -102,17 +94,17 @@ "+\t\text-mic-en-gpios = <&gpio 185 0>;\n" "+\t};\n" "+\n" - "+\tserial@70006300 {\n" + "+\tserial at 70006300 {\n" "+\t\tclock-frequency = < 216000000 >;\n" "+\t};\n" "+\n" - "+\tsdhci@c8000200 {\n" + "+\tsdhci at c8000200 {\n" "+\t\tgpios = <&gpio 69 0>, /* cd, gpio PI5 */\n" "+\t\t\t<&gpio 57 0>, /* wp, gpio PH1 */\n" "+\t\t\t<&gpio 155 0>; /* power, gpio PT3 */\n" "+\t};\n" "+\n" - "+\tsdhci@c8000600 {\n" + "+\tsdhci at c8000600 {\n" "+\t\tgpios = <&gpio 58 0>, /* cd, gpio PH2 */\n" "+\t\t\t<&gpio 59 0>, /* wp, gpio PH3 */\n" "+\t\t\t<&gpio 70 0>; /* power, gpio PI6 */\n" @@ -142,11 +134,11 @@ "+\t\treg = < 0x00000000 0x40000000 >;\n" "+\t};\n" "+\n" - "+\tserial@70006300 {\n" + "+\tserial at 70006300 {\n" "+\t\tclock-frequency = < 216000000 >;\n" "+\t};\n" "+\n" - "+\tsdhci@c8000400 {\n" + "+\tsdhci at c8000400 {\n" "+\t\tgpios = <&gpio 69 0>, /* cd, gpio PI5 */\n" "+\t\t\t<&gpio 57 0>, /* wp, gpio PH1 */\n" "+\t\t\t<&gpio 70 0>; /* power, gpio PI6 */\n" @@ -171,7 +163,7 @@ "+\t\t#size-cells = <1>;\n" "+\t\tranges;\n" "+\n" - "+\t\tintc: interrupt-controller@50041000 {\n" + "+\t\tintc: interrupt-controller at 50041000 {\n" "+\t\t\tcompatible = \"nvidia,tegra20-gic\", \"arm,gic\";\n" "+\t\t\tinterrupt-controller;\n" "+\t\t\t#interrupt-cells = <1>;\n" @@ -181,7 +173,7 @@ "+\t};\n" "+\n" "+\n" - "+\ti2c@7000c000 {\n" + "+\ti2c at 7000c000 {\n" "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <0>;\n" "+\t\tcompatible = \"nvidia,tegra20-i2c\";\n" @@ -189,7 +181,7 @@ "+\t\tinterrupts = < 70 >;\n" "+\t};\n" "+\n" - "+\ti2c@7000c400 {\n" + "+\ti2c at 7000c400 {\n" "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <0>;\n" "+\t\tcompatible = \"nvidia,tegra20-i2c\";\n" @@ -197,7 +189,7 @@ "+\t\tinterrupts = < 116 >;\n" "+\t};\n" "+\n" - "+\ti2c@7000c500 {\n" + "+\ti2c at 7000c500 {\n" "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <0>;\n" "+\t\tcompatible = \"nvidia,tegra20-i2c\";\n" @@ -205,7 +197,7 @@ "+\t\tinterrupts = < 124 >;\n" "+\t};\n" "+\n" - "+\ti2c@7000d000 {\n" + "+\ti2c at 7000d000 {\n" "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <0>;\n" "+\t\tcompatible = \"nvidia,tegra20-i2c\";\n" @@ -213,7 +205,7 @@ "+\t\tinterrupts = < 85 >;\n" "+\t};\n" "+\n" - "+\ti2s@70002800 {\n" + "+\ti2s at 70002800 {\n" "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <0>;\n" "+\t\tcompatible = \"nvidia,tegra20-i2s\";\n" @@ -222,7 +214,7 @@ "+\t\tdma-channel = < 2 >;\n" "+\t};\n" "+\n" - "+\ti2s@70002a00 {\n" + "+\ti2s at 70002a00 {\n" "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <0>;\n" "+\t\tcompatible = \"nvidia,tegra20-i2s\";\n" @@ -231,14 +223,14 @@ "+\t\tdma-channel = < 1 >;\n" "+\t};\n" "+\n" - "+\tdas@70000c00 {\n" + "+\tdas at 70000c00 {\n" "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <0>;\n" "+\t\tcompatible = \"nvidia,tegra20-das\";\n" "+\t\treg = <0x70000c00 0x80>;\n" "+\t};\n" "+\n" - "+\tgpio: gpio@6000d000 {\n" + "+\tgpio: gpio at 6000d000 {\n" "+\t\tcompatible = \"nvidia,tegra20-gpio\";\n" "+\t\treg = < 0x6000d000 0x1000 >;\n" "+\t\tinterrupts = < 64 65 66 67 87 119 121 >;\n" @@ -246,60 +238,60 @@ "+\t\tgpio-controller;\n" "+\t};\n" "+\n" - "+\tserial@70006000 {\n" + "+\tserial at 70006000 {\n" "+\t\tcompatible = \"nvidia,tegra20-uart\";\n" "+\t\treg = <0x70006000 0x40>;\n" "+\t\treg-shift = <2>;\n" "+\t\tinterrupts = < 68 >;\n" "+\t};\n" "+\n" - "+\tserial@70006040 {\n" + "+\tserial at 70006040 {\n" "+\t\tcompatible = \"nvidia,tegra20-uart\";\n" "+\t\treg = <0x70006040 0x40>;\n" "+\t\treg-shift = <2>;\n" "+\t\tinterrupts = < 69 >;\n" "+\t};\n" "+\n" - "+\tserial@70006200 {\n" + "+\tserial at 70006200 {\n" "+\t\tcompatible = \"nvidia,tegra20-uart\";\n" "+\t\treg = <0x70006200 0x100>;\n" "+\t\treg-shift = <2>;\n" "+\t\tinterrupts = < 78 >;\n" "+\t};\n" "+\n" - "+\tserial@70006300 {\n" + "+\tserial at 70006300 {\n" "+\t\tcompatible = \"nvidia,tegra20-uart\";\n" "+\t\treg = <0x70006300 0x100>;\n" "+\t\treg-shift = <2>;\n" "+\t\tinterrupts = < 122 >;\n" "+\t};\n" "+\n" - "+\tserial@70006400 {\n" + "+\tserial at 70006400 {\n" "+\t\tcompatible = \"nvidia,tegra20-uart\";\n" "+\t\treg = <0x70006400 0x100>;\n" "+\t\treg-shift = <2>;\n" "+\t\tinterrupts = < 123 >;\n" "+\t};\n" "+\n" - "+\tsdhci@c8000000 {\n" + "+\tsdhci at c8000000 {\n" "+\t\tcompatible = \"nvidia,tegra20-sdhci\";\n" "+\t\treg = <0xc8000000 0x200>;\n" "+\t\tinterrupts = < 46 >;\n" "+\t};\n" "+\n" - "+\tsdhci@c8000200 {\n" + "+\tsdhci at c8000200 {\n" "+\t\tcompatible = \"nvidia,tegra20-sdhci\";\n" "+\t\treg = <0xc8000200 0x200>;\n" "+\t\tinterrupts = < 47 >;\n" "+\t};\n" "+\n" - "+\tsdhci@c8000400 {\n" + "+\tsdhci at c8000400 {\n" "+\t\tcompatible = \"nvidia,tegra20-sdhci\";\n" "+\t\treg = <0xc8000400 0x200>;\n" "+\t\tinterrupts = < 51 >;\n" "+\t};\n" "+\n" - "+\tsdhci@c8000600 {\n" + "+\tsdhci at c8000600 {\n" "+\t\tcompatible = \"nvidia,tegra20-sdhci\";\n" "+\t\treg = <0xc8000600 0x200>;\n" "+\t\tinterrupts = < 63 >;\n" @@ -471,4 +463,4 @@ "+\t.dt_compat\t= tegra_dt_board_compat,\n" +MACHINE_END -d8663500b48ad7bcd8253c0eb6e2cef5cbe04f210bc3de55f2a9e136337b9620 +ad1f1773912fc5f3be37bb8306b378c9da0cb741415a672b56f686356ae96b53
diff --git a/a/1.txt b/N2/1.txt index f648ad3..5d35cff 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -4,7 +4,7 @@ a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. -Signed-off-by: Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org> +Signed-off-by: Grant Likely <grant.likely@secretlab.ca> --- Hi all, diff --git a/a/content_digest b/N2/content_digest index d911758..aa293c7 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,15 +1,15 @@ - "From\0Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>\0" + "From\0Grant Likely <grant.likely@secretlab.ca>\0" "Subject\0[PATCH] arm/dt: tegra devicetree support\0" "Date\0Tue, 19 Jul 2011 17:43:17 -0600\0" - "To\0Erik Gilling <konkers-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org>" - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - Colin Cross <ccross-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org> - Olof Johansson <olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org> - " linux-arm-kernel@list\0" - "Cc\0Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>" - swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org - " Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>\0" + "To\0Erik Gilling <konkers@android.com>" + linux-kernel@vger.kernel.org + linux-tegra@vger.kernel.org + Colin Cross <ccross@android.com> + Olof Johansson <olof@lixom.net> + " linux-arm-kernel@lists.infradead.org\0" + "Cc\0Russell King <linux@arm.linux.org.uk>" + swarren@nvidia.com + " Arnd Bergmann <arnd@arndb.de>\0" "\00:1\0" "b\0" "Everything required to populate NVIDIA Tegra devices from the device\n" @@ -18,7 +18,7 @@ "but it will be refined in follow on patches to configure clocks and\n" "pin IO from the device tree also.\n" "\n" - "Signed-off-by: Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>\n" + "Signed-off-by: Grant Likely <grant.likely@secretlab.ca>\n" "---\n" "\n" "Hi all,\n" @@ -471,4 +471,4 @@ "+\t.dt_compat\t= tegra_dt_board_compat,\n" +MACHINE_END -d8663500b48ad7bcd8253c0eb6e2cef5cbe04f210bc3de55f2a9e136337b9620 +12ba1b55ca2df340cd25f2f548f7472e4f32313d035b0f79ebd73e16647aa514
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