diff for duplicates of <20110827160746.GA11076@kroah.com> diff --git a/a/1.txt b/N1/1.txt index 7338621..413f87f 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -2,7 +2,7 @@ On Sat, Aug 27, 2011 at 11:33:26PM +0800, Ming Lei wrote: > Hi, > > On Sat, Aug 27, 2011 at 11:13 PM, Greg KH <greg@kroah.com> wrote: -> > On Sat, Aug 27, 2011 at 10:48:35PM +0800, ming.lei@canonical.com wrote: +> > On Sat, Aug 27, 2011 at 10:48:35PM +0800, ming.lei at canonical.com wrote: > >> From: Ming Lei <ming.lei@canonical.com> > >> > >> This patch fixs one performance bug on ARM Cortex A9 dual core platform, @@ -13,8 +13,8 @@ On Sat, Aug 27, 2011 at 11:33:26PM +0800, Ming Lei wrote: > >> 'dummy->hw_token = token;' after mb() is added just for obeying > >> correct mb() usage. > > -> > Really? A mb() should not be flushing any caches, it's just a memory -> > barrier. Or is ARM somehow "special" in this way? +> > Really? ?A mb() should not be flushing any caches, it's just a memory +> > barrier. ?Or is ARM somehow "special" in this way? > > As Santosh pointed out, mb on ARM will flush L2 write buffer. The > description here is wrong. @@ -42,30 +42,30 @@ confirm this? > > > >> Signed-off-by: Ming Lei <ming.lei@canonical.com> > >> --- -> >> drivers/usb/host/ehci-q.c | 14 ++++++++++++++ -> >> 1 files changed, 14 insertions(+), 0 deletions(-) +> >> ?drivers/usb/host/ehci-q.c | ? 14 ++++++++++++++ +> >> ?1 files changed, 14 insertions(+), 0 deletions(-) > >> > >> diff --git a/drivers/usb/host/ehci-q.c b/drivers/usb/host/ehci-q.c > >> index 0917e3a..65b5021 100644 > >> --- a/drivers/usb/host/ehci-q.c > >> +++ b/drivers/usb/host/ehci-q.c > >> @@ -1082,6 +1082,20 @@ static struct ehci_qh *qh_append_tds ( -> >> wmb (); -> >> dummy->hw_token = token; +> >> ? ? ? ? ? ? ? ? ? ? ? wmb (); +> >> ? ? ? ? ? ? ? ? ? ? ? dummy->hw_token = token; > >> -> >> + /* The mb() below is added to make sure that -> >> + * 'token' can be writen into qtd, so that ehci -> >> + * HC can see the up-to-date qtd descriptor. On -> >> + * some archs(at least on ARM Cortex A9 dual core), -> >> + * writing into coherenet memory doesn't mean the -> >> + * value written can reach physical memory -> >> + * immediately, and the value may be buffered -> >> + * inside L2 cache. 'dummy->hw_token = token;' -> >> + * after mb() is added for obeying correct mb() -> >> + * usage. -> >> + * */ -> >> + mb(); -> >> + token = dummy->hw_token; +> >> + ? ? ? ? ? ? ? ? ? ? /* The mb() below is added to make sure that +> >> + ? ? ? ? ? ? ? ? ? ? ?* 'token' can be writen into qtd, so that ehci +> >> + ? ? ? ? ? ? ? ? ? ? ?* HC can see the up-to-date qtd descriptor. On +> >> + ? ? ? ? ? ? ? ? ? ? ?* some archs(at least on ARM Cortex A9 dual core), +> >> + ? ? ? ? ? ? ? ? ? ? ?* writing into coherenet memory doesn't mean the +> >> + ? ? ? ? ? ? ? ? ? ? ?* value written can reach physical memory +> >> + ? ? ? ? ? ? ? ? ? ? ?* immediately, and the value may be buffered +> >> + ? ? ? ? ? ? ? ? ? ? ?* inside L2 cache. 'dummy->hw_token = token;' +> >> + ? ? ? ? ? ? ? ? ? ? ?* after mb() is added for obeying correct mb() +> >> + ? ? ? ? ? ? ? ? ? ? ?* usage. +> >> + ? ? ? ? ? ? ? ? ? ? ?* */ +> >> + ? ? ? ? ? ? ? ? ? ? mb(); +> >> + ? ? ? ? ? ? ? ? ? ? token = dummy->hw_token; > > > > Your comment does not match the code, so something is wrong here. > diff --git a/a/content_digest b/N1/content_digest index f09e9d4..84dada4 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,21 +1,17 @@ "ref\01314456515-16419-1-git-send-email-ming.lei@canonical.com\0" "ref\020110827151317.GA10013@kroah.com\0" "ref\0CACVXFVM_p_XPyOOgz7kbEo93SCCxPa4X_vjYGm+fUGMPSFM4EA@mail.gmail.com\0" - "From\0Greg KH <greg@kroah.com>\0" - "Subject\0Re: [PATCH] usb: ehci: fix update qtd->token in qh_append_tds\0" + "From\0greg@kroah.com (Greg KH)\0" + "Subject\0[PATCH] usb: ehci: fix update qtd->token in qh_append_tds\0" "Date\0Sat, 27 Aug 2011 09:07:46 -0700\0" - "To\0Ming Lei <ming.lei@canonical.com>\0" - "Cc\0linux-omap@vger.kernel.org" - linux-usb@vger.kernel.org - stern@rowland.harvard.edu - " linux-arm-kernel@lists.infradead.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Sat, Aug 27, 2011 at 11:33:26PM +0800, Ming Lei wrote:\n" "> Hi,\n" "> \n" "> On Sat, Aug 27, 2011 at 11:13 PM, Greg KH <greg@kroah.com> wrote:\n" - "> > On Sat, Aug 27, 2011 at 10:48:35PM +0800, ming.lei@canonical.com wrote:\n" + "> > On Sat, Aug 27, 2011 at 10:48:35PM +0800, ming.lei at canonical.com wrote:\n" "> >> From: Ming Lei <ming.lei@canonical.com>\n" "> >>\n" "> >> This patch fixs one performance bug on ARM Cortex A9 dual core platform,\n" @@ -26,8 +22,8 @@ "> >> 'dummy->hw_token = token;' after mb() is added just for obeying\n" "> >> correct mb() usage.\n" "> >\n" - "> > Really? \302\240A mb() should not be flushing any caches, it's just a memory\n" - "> > barrier. \302\240Or is ARM somehow \"special\" in this way?\n" + "> > Really? ?A mb() should not be flushing any caches, it's just a memory\n" + "> > barrier. ?Or is ARM somehow \"special\" in this way?\n" "> \n" "> As Santosh pointed out, mb on ARM will flush L2 write buffer. The\n" "> description here is wrong.\n" @@ -55,30 +51,30 @@ "> >\n" "> >> Signed-off-by: Ming Lei <ming.lei@canonical.com>\n" "> >> ---\n" - "> >> \302\240drivers/usb/host/ehci-q.c | \302\240 14 ++++++++++++++\n" - "> >> \302\2401 files changed, 14 insertions(+), 0 deletions(-)\n" + "> >> ?drivers/usb/host/ehci-q.c | ? 14 ++++++++++++++\n" + "> >> ?1 files changed, 14 insertions(+), 0 deletions(-)\n" "> >>\n" "> >> diff --git a/drivers/usb/host/ehci-q.c b/drivers/usb/host/ehci-q.c\n" "> >> index 0917e3a..65b5021 100644\n" "> >> --- a/drivers/usb/host/ehci-q.c\n" "> >> +++ b/drivers/usb/host/ehci-q.c\n" "> >> @@ -1082,6 +1082,20 @@ static struct ehci_qh *qh_append_tds (\n" - "> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 wmb ();\n" - "> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 dummy->hw_token = token;\n" + "> >> ? ? ? ? ? ? ? ? ? ? ? wmb ();\n" + "> >> ? ? ? ? ? ? ? ? ? ? ? dummy->hw_token = token;\n" "> >>\n" - "> >> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 /* The mb() below is added to make sure that\n" - "> >> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240* 'token' can be writen into qtd, so that ehci\n" - "> >> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240* HC can see the up-to-date qtd descriptor. On\n" - "> >> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240* some archs(at least on ARM Cortex A9 dual core),\n" - "> >> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240* writing into coherenet memory doesn't mean the\n" - "> >> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240* value written can reach physical memory\n" - "> >> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240* immediately, and the value may be buffered\n" - "> >> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240* inside L2 cache. 'dummy->hw_token = token;'\n" - "> >> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240* after mb() is added for obeying correct mb()\n" - "> >> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240* usage.\n" - "> >> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240* */\n" - "> >> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 mb();\n" - "> >> + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 token = dummy->hw_token;\n" + "> >> + ? ? ? ? ? ? ? ? ? ? /* The mb() below is added to make sure that\n" + "> >> + ? ? ? ? ? ? ? ? ? ? ?* 'token' can be writen into qtd, so that ehci\n" + "> >> + ? ? ? ? ? ? ? ? ? ? ?* HC can see the up-to-date qtd descriptor. On\n" + "> >> + ? ? ? ? ? ? ? ? ? ? ?* some archs(at least on ARM Cortex A9 dual core),\n" + "> >> + ? ? ? ? ? ? ? ? ? ? ?* writing into coherenet memory doesn't mean the\n" + "> >> + ? ? ? ? ? ? ? ? ? ? ?* value written can reach physical memory\n" + "> >> + ? ? ? ? ? ? ? ? ? ? ?* immediately, and the value may be buffered\n" + "> >> + ? ? ? ? ? ? ? ? ? ? ?* inside L2 cache. 'dummy->hw_token = token;'\n" + "> >> + ? ? ? ? ? ? ? ? ? ? ?* after mb() is added for obeying correct mb()\n" + "> >> + ? ? ? ? ? ? ? ? ? ? ?* usage.\n" + "> >> + ? ? ? ? ? ? ? ? ? ? ?* */\n" + "> >> + ? ? ? ? ? ? ? ? ? ? mb();\n" + "> >> + ? ? ? ? ? ? ? ? ? ? token = dummy->hw_token;\n" "> >\n" "> > Your comment does not match the code, so something is wrong here.\n" "> \n" @@ -90,4 +86,4 @@ "\n" greg k-h -ed22cc3056d8ea79e8eb4f2458743ce00ea3b00ef5a7dd6c5cfd3e9e4282262a +8ddbabbcaf5292c90e364f5ddd312b05a2b6fcbddabfaaae5c21ae373ee9de04
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