diff for duplicates of <20110914091531.GA2104@arm.com> diff --git a/a/1.txt b/N1/1.txt index 4e89bbf..bf83207 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -17,25 +17,25 @@ On Tue, Sep 13, 2011 at 06:46:48PM -0700, Colin Cross wrote: > >> Signed-off-by: Dave Martin <dave.martin@linaro.org> > >> --- > >> -> >> I make assumptions about the bootloader in this patch. If someone with +> >> I make assumptions about the bootloader in this patch. ?If someone with > >> Tegra knowledge can please comment and/or test, that would be much > >> appreciated, thanks. > >> -> >> arch/arm/mach-tegra/headsmp.S | 1 - -> >> 1 files changed, 0 insertions(+), 1 deletions(-) +> >> ?arch/arm/mach-tegra/headsmp.S | ? ?1 - +> >> ?1 files changed, 0 insertions(+), 1 deletions(-) > >> > >> diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S > >> index b5349b2..6ec4790 100644 > >> --- a/arch/arm/mach-tegra/headsmp.S > >> +++ b/arch/arm/mach-tegra/headsmp.S > >> @@ -48,7 +48,6 @@ ENTRY(v7_invalidate_l1) -> >> ENDPROC(v7_invalidate_l1) +> >> ?ENDPROC(v7_invalidate_l1) > >> -> >> ENTRY(tegra_secondary_startup) -> >> - msr cpsr_fsxc, #0xd3 -> >> bl v7_invalidate_l1 -> >> mrc p15, 0, r0, c0, c0, 5 -> >> and r0, r0, #15 +> >> ?ENTRY(tegra_secondary_startup) +> >> - ? ? msr ? ? cpsr_fsxc, #0xd3 +> >> ? ? ? ? ?bl ? ? ?v7_invalidate_l1 +> >> ? ? ? mrc ? ? p15, 0, r0, c0, c0, 5 +> >> ? ? ? ? ?and ?r0, r0, #15 > > > > My rationale here is that the CPU boots straight into the > > correct mode -- if there is any boot code before we get here, @@ -45,7 +45,7 @@ On Tue, Sep 13, 2011 at 06:46:48PM -0700, Colin Cross wrote: > > > > If that feels unsafe however, we should still to be able to write > > -> > cpsid aif, #SVC_MODE +> > ? ? ? ?cpsid ? aif, #SVC_MODE > > > > (which is the compact v6/v7-compatible way to set all the interrupt > > mask bits and get into a specific mode) diff --git a/a/content_digest b/N1/content_digest index 1803d29..fbac380 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,12 +1,10 @@ "ref\01315411253-17559-1-git-send-email-dave.martin@linaro.org\0" "ref\020110912165222.GE2020@arm.com\0" "ref\0CAMbhsRSoSYhuqPC+SmCNk4dseok0vs02su0kihKNqXGpCvUvSg@mail.gmail.com\0" - "From\0Dave Martin <dave.martin@linaro.org>\0" - "Subject\0Re: [PATCH] ARM: tegra: Remove redundant change to the CPSR in headsmp.S\0" + "From\0dave.martin@linaro.org (Dave Martin)\0" + "Subject\0[PATCH] ARM: tegra: Remove redundant change to the CPSR in headsmp.S\0" "Date\0Wed, 14 Sep 2011 10:15:32 +0100\0" - "To\0Colin Cross <ccross@android.com>\0" - "Cc\0linux-tegra@vger.kernel.org" - " linux-arm-kernel@lists.infradead.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Tue, Sep 13, 2011 at 06:46:48PM -0700, Colin Cross wrote:\n" @@ -28,25 +26,25 @@ "> >> Signed-off-by: Dave Martin <dave.martin@linaro.org>\n" "> >> ---\n" "> >>\n" - "> >> I make assumptions about the bootloader in this patch. \302\240If someone with\n" + "> >> I make assumptions about the bootloader in this patch. ?If someone with\n" "> >> Tegra knowledge can please comment and/or test, that would be much\n" "> >> appreciated, thanks.\n" "> >>\n" - "> >> \302\240arch/arm/mach-tegra/headsmp.S | \302\240 \302\2401 -\n" - "> >> \302\2401 files changed, 0 insertions(+), 1 deletions(-)\n" + "> >> ?arch/arm/mach-tegra/headsmp.S | ? ?1 -\n" + "> >> ?1 files changed, 0 insertions(+), 1 deletions(-)\n" "> >>\n" "> >> diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S\n" "> >> index b5349b2..6ec4790 100644\n" "> >> --- a/arch/arm/mach-tegra/headsmp.S\n" "> >> +++ b/arch/arm/mach-tegra/headsmp.S\n" "> >> @@ -48,7 +48,6 @@ ENTRY(v7_invalidate_l1)\n" - "> >> \302\240ENDPROC(v7_invalidate_l1)\n" + "> >> ?ENDPROC(v7_invalidate_l1)\n" "> >>\n" - "> >> \302\240ENTRY(tegra_secondary_startup)\n" - "> >> - \302\240 \302\240 msr \302\240 \302\240 cpsr_fsxc, #0xd3\n" - "> >> \302\240 \302\240 \302\240 \302\240 \302\240bl \302\240 \302\240 \302\240v7_invalidate_l1\n" - "> >> \302\240 \302\240 \302\240 mrc \302\240 \302\240 p15, 0, r0, c0, c0, 5\n" - "> >> \302\240 \302\240 \302\240 \302\240 \302\240and \302\240r0, r0, #15\n" + "> >> ?ENTRY(tegra_secondary_startup)\n" + "> >> - ? ? msr ? ? cpsr_fsxc, #0xd3\n" + "> >> ? ? ? ? ?bl ? ? ?v7_invalidate_l1\n" + "> >> ? ? ? mrc ? ? p15, 0, r0, c0, c0, 5\n" + "> >> ? ? ? ? ?and ?r0, r0, #15\n" "> >\n" "> > My rationale here is that the CPU boots straight into the\n" "> > correct mode -- if there is any boot code before we get here,\n" @@ -56,7 +54,7 @@ "> >\n" "> > If that feels unsafe however, we should still to be able to write\n" "> >\n" - "> > \302\240 \302\240 \302\240 \302\240cpsid \302\240 aif, #SVC_MODE\n" + "> > ? ? ? ?cpsid ? aif, #SVC_MODE\n" "> >\n" "> > (which is the compact v6/v7-compatible way to set all the interrupt\n" "> > mask bits and get into a specific mode)\n" @@ -101,4 +99,4 @@ "Cheers\n" ---Dave -67ce811bdb0b49dd24a6d492408d78cb9d61f8ff24bf4b78def32ab0519d36b4 +ab6c19de757850dec86a12b56e8508f94d4123501bf88d4110db771e24bc53da
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