From: Daniel Vetter <daniel@ffwll.ch>
To: Kenneth Graunke <kenneth@whitecape.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Use PIPE_CONTROL for flushing on gen6+.
Date: Mon, 26 Sep 2011 22:31:56 +0200 [thread overview]
Message-ID: <20110926203156.GE2804@phenom.ffwll.local> (raw)
In-Reply-To: <1317063563-1526-1-git-send-email-kenneth@whitecape.org>
On Mon, Sep 26, 2011 at 11:59:23AM -0700, Kenneth Graunke wrote:
> +static int
> +gen6_render_ring_flush(struct intel_ring_buffer *ring,
> + u32 invalidate_domains, u32 flush_domains)
> +{
> + u32 flags = 0;
> + struct pipe_control *pc = ring->private;
> + u32 scratch_addr = pc->gtt_offset + 128;
> + int ret;
> +
> + /* Force SNB workarounds for PIPE_CONTROL flushes */
> + intel_emit_post_sync_nonzero_flush(ring);
> +
> + /* Just flush everything for now */
> + flags |= PIPE_CONTROL_WC_FLUSH;
> + flags |= PIPE_CONTROL_IS_FLUSH;
> + flags |= PIPE_CONTROL_TC_FLUSH;
> + flags |= PIPE_CONTROL_DEPTH_FLUSH;
> + flags |= PIPE_CONTROL_VFC;
Any reason you're not also setting the constant cache and state cache
invalidate bits?
-Daniel
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
next prev parent reply other threads:[~2011-09-26 20:31 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-09-26 18:59 [PATCH] drm/i915: Use PIPE_CONTROL for flushing on gen6+ Kenneth Graunke
2011-09-26 19:16 ` Chris Wilson
2011-09-26 19:23 ` Daniel Vetter
2011-09-26 19:43 ` Chris Wilson
2011-09-26 20:15 ` Keith Packard
2011-09-26 20:21 ` Kenneth Graunke
2011-09-26 20:31 ` Daniel Vetter [this message]
2011-09-26 20:38 ` Kenneth Graunke
2011-09-26 22:25 ` Eric Anholt
2011-10-03 20:00 ` Jesse Barnes
2011-10-03 21:14 ` Keith Packard
2011-10-03 21:21 ` Jesse Barnes
2011-10-03 22:59 ` Eric Anholt
2011-10-03 23:16 ` Jesse Barnes
-- strict thread matches above, loose matches on Subject: below --
2011-10-11 21:41 [PATCH 3/3] " Daniel Vetter
2011-10-16 8:23 ` [PATCH] " Daniel Vetter
2011-10-17 1:27 ` Ben Widawsky
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