From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: Re: [PATCH 3/3] drm/i915: Use PIPE_CONTROL for flushing on gen6+. Date: Thu, 6 Oct 2011 05:15:23 +0000 Message-ID: <20111006051523.GA8097@cloud01> References: <1317708160-1761-1-git-send-email-kenneth@whitecape.org> <1317708160-1761-3-git-send-email-kenneth@whitecape.org> <20111005155713.6e2f0c6c@bwidawsk.net> <87zkhf2avg.fsf@eliezer.anholt.net> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0353405874==" Return-path: Received: from cloud01.chad-versace.us (184-106-247-128.static.cloud-ips.com [184.106.247.128]) by gabe.freedesktop.org (Postfix) with ESMTP id 596E69E744 for ; Wed, 5 Oct 2011 22:11:40 -0700 (PDT) In-Reply-To: <87zkhf2avg.fsf@eliezer.anholt.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Eric Anholt Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0353405874== Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="YZ5djTAD1cGYuMQK" Content-Disposition: inline --YZ5djTAD1cGYuMQK Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Oct 05, 2011 at 05:59:31PM -0700, Eric Anholt wrote: > On Wed, 5 Oct 2011 15:57:13 -0700, Ben Widawsky wrote: > > I think we also want a TLB invalidate here, bit 18. This requires anot= her > > workaround before issuing this flush: We need 2 Store Data Commands (su= ch as > > MI_STORE_DATA_IMM or MI_STORE_DATA_INDEX) before sending PIPE_CONTROL w= / stall > > (20) and TLB inv bit (18) set >=20 > From the docs for GFX_MODE: >=20 > "This field controls the invalidation if the TLB cache inside the > hardware. When enabled this bit limits the invalidation of the TLB > only to batch buffer boundaries or to pipe_control commands which > have the TLB invalidation bit set. If disabled, the TLB caches are > flushed for every full flush of the pipeline" >=20 > We're already getting TLB invalidate at batchbuffer boundaries > (actually, even more: every pipeline stall, since that bit is 0 on my > hardware). What would we need this new flush for? Does this only mean after each batchbuffer (MI_BATCH_BUFFER_END) or also before actually jumping to the location at MI_BATCH_BUFFER_START? If so, what happens when we map or unmap, in between batches? Won't the TLBs need to be flushed in between? Also, wouldn't it be nice for the kernel to flush TLBs without having to submit a batch (no specific use case in mind for this)?=20 Ben --YZ5djTAD1cGYuMQK Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAEBAgAGBQJOjTlqAAoJEL9nTIiJEj0pMgoIAM6Iq7qpk2rWj2uVZHkU6GNK inuB44Rbfls4AijxnbZGk5uDKeb/8KZaKdzdpS35ZIVVRqa3bxxRkf7iJd3ii9Tv XoXnkeWvgbLi3I9etQomffq9iqEzQmt/NqFs71bTJUw0fxKHAtsyMQQaCMBWdeTe Naq+2OIY/TDMsmT9XdTJoLWFB/FH2gMU7+ztVIyUWG5QZv1SS1Q5k3ujJqN9c9hG g3XhOBfVAtHUMTI7gpwfuXXIWn9llYne+qIC9DJLzXlOcjmBKNqJt+dh3htt6hY/ F9YoY8c5NnADIHv95u85RLpskSsaHC0N75IshADhMVla8pkpnjkQAgyPT1QbLx0= =WFTa -----END PGP SIGNATURE----- --YZ5djTAD1cGYuMQK-- --===============0353405874== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0353405874==--