[U-Boot] [PATCH 1/2] Tegra2: Make XTal speed configurable

[Marek Vasut <marek.vasut@gmail.com>]

On Wednesday, October 12, 2011 11:17:07 PM Simon Glass wrote:
> Hi Marek,
> 
> On Wed, Oct 12, 2011 at 4:19 AM, Marek Vasut <marek.vasut@gmail.com> wrote:
> > On Wednesday, October 12, 2011 02:30:57 AM Simon Glass wrote:
> >> Hi Marek,
> >> 
> >> On Wed, Oct 5, 2011 at 10:05 AM, Marek Vasut <marek.vasut@gmail.com> wrote:
> >> > On Wednesday, October 05, 2011 04:10:56 PM Simon Glass wrote:
> >> >> Hi Marek,
> >> >> 
> >> >> On Fri, Sep 30, 2011 at 5:12 PM, Marek Vasut <marek.vasut@gmail.com> 
wrote:
> >> >> > The Toradex T20 module uses 13MHz Xtal, so make the Xtal speed
> >> >> > configurable.
> >> >> > 
> >> >> > Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
> >> >> > Cc: Simon Glass <sjg@chromium.org>
> >> >> > Cc: Ben Warren <biggerbadderben@gmail.com>
> >> >> > Cc: Tom Warren <twarren.nvidia@gmail.com>
> >> >> > Cc: Stephen Warren <swarren@nvidia.com>
> >> >> > ---
> >> >> >  arch/arm/cpu/armv7/tegra2/ap20.c |    9 +++++++--
> >> >> >  1 files changed, 7 insertions(+), 2 deletions(-)
> >> >> > 
> >> >> > diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c
> >> >> > b/arch/arm/cpu/armv7/tegra2/ap20.c index dc5f984..71d9f26 100644
> >> >> > --- a/arch/arm/cpu/armv7/tegra2/ap20.c
> >> >> > +++ b/arch/arm/cpu/armv7/tegra2/ap20.c
> >> >> > @@ -31,6 +31,11 @@
> >> >> >  #include <asm/arch/scu.h>
> >> >> >  #include <common.h>
> >> >> > 
> >> >> > +/* The default XTal is 12MHz, some boards might use 13MHz one
> >> >> > though */ +#ifndef        CONFIG_SYS_TEGRA2_XTAL_MHZ
> >> >> > +#define        CONFIG_SYS_TEGRA2_XTAL_MHZ      12
> >> >> > +#endif
> >> >> > +
> >> >> >  u32 s_first_boot = 1;
> >> >> > 
> >> >> >  void init_pllx(void)
> >> >> > @@ -46,8 +51,8 @@ void init_pllx(void)
> >> >> >        /* Set PLLX_MISC */
> >> >> >        writel(1 << PLL_CPCON_SHIFT, &pll->pll_misc);
> >> >> > 
> >> >> > -       /* Use 12MHz clock here */
> >> >> > -       reg = PLL_BYPASS_MASK | (12 << PLL_DIVM_SHIFT);
> >> >> > +       /* Use 13MHz clock here */
> >> >> 
> >> >> Change comment?
> >> >> 
> >> >> > +       reg = PLL_BYPASS_MASK | (CONFIG_SYS_TEGRA2_XTAL_MHZ <<
> >> >> > PLL_DIVM_SHIFT); reg |= 1000 << PLL_DIVN_SHIFT;
> >> >> >        writel(reg, &pll->pll_base);
> >> >> > 
> >> >> > --
> >> >> > 1.7.5.4
> >> >> 
> >> >> Regards,
> >> >> Simon
> >> > 
> >> > Hi Simon, I'll probably also change the board.c to support this. But
> >> > then, can't the board.c be moved to arch/arm/cpu/armv7/tegra... and
> >> > it's functions exported via standard header ? Cheers
> >> 
> >> Which board.c do you mean and which change do you need to make?
> > 
> > Hi Simon,
> > 
> > board/nvidia/common/board.c
> > 
> > same as this patch does .
> 
> Well there are several files called board.c:
> 
> board/nvidia/common/board.c - Common things for Nvidia boards
> arch/arm/lib/board.c - Generic ARM things
> arch/arm/cpu/armv7/tegra2/board.c - Generic Tegra things
> 
> Since this is to do with Tegra, I think it should stay where it is in
> ap20.c and you should just add a config. For now
> arch/arm/cpu/armv7/tegra2/board.c just deals with DRAM.
> 

Hi Simon,

the same register gets set in both boards/.../board.c and ap20.c ... which 
itself is a bit suspicious.

Cheers