From: Robin Holt <holt@sgi.com>
To: Joerg Roedel <joerg.roedel@amd.com>
Cc: Andrea Arcangeli <aarcange@redhat.com>,
Rik van Riel <riel@redhat.com>,
akpm@linux-foundation.org,
Hugh Dickins <hugh.dickins@tiscali.co.uk>,
Mel Gorman <mel@csn.ul.ie>, Nick Piggin <npiggin@kernel.dk>,
linux-mm@kvack.org, linux-kernel@vger.kernel.org,
joro@8bytes.org
Subject: Re: [RFC][PATCH 0/3] Add support for non-CPU TLBs in MMU-Notifiers
Date: Wed, 2 Nov 2011 04:46:02 -0500 [thread overview]
Message-ID: <20111102094601.GN28536@sgi.com> (raw)
In-Reply-To: <1319199708-17777-1-git-send-email-joerg.roedel@amd.com>
On Fri, Oct 21, 2011 at 02:21:45PM +0200, Joerg Roedel wrote:
> Hi,
>
> this is my first attempt to add support for non-CPU TLBs to the
> MMU-Notifier framework. This will be used by the AMD IOMMU driver for
> the next generation of hardware. The next version of the AMD IOMMU can
> walk page-tables in AMD64 long-mode format (with setting
> accessed/dirty-bits atomically) and save the translations in its own
> TLB. Page faulting for IO devices is supported too. This will be used to
> let hardware devices share page-tables with CPU processes and access
> their memory directly. Please look at
>
> http://support.amd.com/us/Processor_TechDocs/48882.pdf
...
Did this patch set get any review or traction? Perhaps you should have
included the linux-mm@kvack.org mailing list.
Robin
WARNING: multiple messages have this Message-ID (diff)
From: Robin Holt <holt@sgi.com>
To: Joerg Roedel <joerg.roedel@amd.com>
Cc: Andrea Arcangeli <aarcange@redhat.com>,
Rik van Riel <riel@redhat.com>,
akpm@linux-foundation.org,
Hugh Dickins <hugh.dickins@tiscali.co.uk>,
Mel Gorman <mel@csn.ul.ie>, Nick Piggin <npiggin@kernel.dk>,
linux-mm@kvack.org, linux-kernel@vger.kernel.org,
joro@8bytes.org
Subject: Re: [RFC][PATCH 0/3] Add support for non-CPU TLBs in MMU-Notifiers
Date: Wed, 2 Nov 2011 04:46:02 -0500 [thread overview]
Message-ID: <20111102094601.GN28536@sgi.com> (raw)
In-Reply-To: <1319199708-17777-1-git-send-email-joerg.roedel@amd.com>
On Fri, Oct 21, 2011 at 02:21:45PM +0200, Joerg Roedel wrote:
> Hi,
>
> this is my first attempt to add support for non-CPU TLBs to the
> MMU-Notifier framework. This will be used by the AMD IOMMU driver for
> the next generation of hardware. The next version of the AMD IOMMU can
> walk page-tables in AMD64 long-mode format (with setting
> accessed/dirty-bits atomically) and save the translations in its own
> TLB. Page faulting for IO devices is supported too. This will be used to
> let hardware devices share page-tables with CPU processes and access
> their memory directly. Please look at
>
> http://support.amd.com/us/Processor_TechDocs/48882.pdf
...
Did this patch set get any review or traction? Perhaps you should have
included the linux-mm@kvack.org mailing list.
Robin
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next prev parent reply other threads:[~2011-11-02 9:46 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-10-21 12:21 [RFC][PATCH 0/3] Add support for non-CPU TLBs in MMU-Notifiers Joerg Roedel
2011-10-21 12:21 ` Joerg Roedel
2011-10-21 12:21 ` [PATCH 1/3] mm: Disable tlb_fast_mode() when mm has notifiers Joerg Roedel
2011-10-21 12:21 ` Joerg Roedel
2011-10-21 12:21 ` [PATCH 2/3] mmu_notifier: Add invalidate_range_free_pages() notifier Joerg Roedel
2011-10-21 12:21 ` Joerg Roedel
2011-10-21 12:21 ` [PATCH 3/3] mmu_notifier: Call " Joerg Roedel
2011-10-21 12:21 ` Joerg Roedel
2011-11-02 9:46 ` Robin Holt [this message]
2011-11-02 9:46 ` [RFC][PATCH 0/3] Add support for non-CPU TLBs in MMU-Notifiers Robin Holt
2011-11-02 9:57 ` Roedel, Joerg
2011-11-02 9:57 ` Roedel, Joerg
2011-11-03 0:07 ` Andrea Arcangeli
2011-11-03 0:07 ` Andrea Arcangeli
2011-11-03 10:18 ` Roedel, Joerg
2011-11-03 10:18 ` Roedel, Joerg
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