From mboxrd@z Thu Jan 1 00:00:00 1970 From: Wei Wang2 Subject: Re: [PATCH 2 of 6] amd iommu: Cleanup iommu pci capabilites detection Date: Fri, 11 Nov 2011 11:16:27 +0100 Message-ID: <201111111116.28286.wei.wang2@amd.com> References: <4b115815bc13e4f2a3a1.1320853857@gran.amd.com> <4EBCF9E30200007800060600@nat28.tlf.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <4EBCF9E30200007800060600@nat28.tlf.novell.com> Content-Disposition: inline List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Jan Beulich Cc: xen-devel@lists.xensource.com List-Id: xen-devel@lists.xenproject.org On Friday 11 November 2011 10:33:07 Jan Beulich wrote: > >>> On 09.11.11 at 16:50, Wei Wang wrote: > > > > # HG changeset patch > > # User Wei Wang > > # Date 1320851997 -3600 > > # Node ID 4b115815bc13e4f2a3a178f3de7477ecf46cb44b > > # Parent 4769713326a876c25bdc0f9d1f90594f90fba9c5 > > amd iommu: Cleanup iommu pci capabilites detection. > > * Define new structure to represent capability block. > > * Remove unnecessary read for unused information. > > * Add sanity check into get_iommu_capabilities. > > * iommu capability offset is 16 bit not 8 bit, fix that. > > Does this imply that the capability can reside in extended config space? > If so, all code paths using this will need revisiting with regard to > extended config space possibly being inaccessible until early Dom0 > initialization. Jan, This is just an inconsistency issue with iommu specification as in IVHD header, it has been defined as 16 bit value. In reality, both current and next generation amd iommu will not have this capability in extended pci config space. Thanks, Wei > Jan > > > Signed-off-by: Wei Wang