From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ira W. Snyder Date: Fri, 11 Nov 2011 09:12:32 -0800 Subject: [U-Boot] [PATCH v3 2/2] mpc85xx: support for Freescale COM Express P2020 In-Reply-To: References: <1320959487-27606-1-git-send-email-iws@ovro.caltech.edu> <1320959487-27606-3-git-send-email-iws@ovro.caltech.edu> <9C248D64-15CB-4B71-9C6B-5559F18B5546@kernel.crashing.org> <20111111165343.GA32482@ovro.caltech.edu> Message-ID: <20111111171232.GB32482@ovro.caltech.edu> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Fri, Nov 11, 2011 at 04:58:17PM +0000, McClintock Matthew-B29882 wrote: > On Fri, Nov 11, 2011 at 10:53 AM, Ira W. Snyder wrote: > >> Does the board really support different DDR freq or is this copy / paste? > >> > > > > The memory is an SODIMM, but the RAM is configured before U-Boot runs by > > the Freescale On-Chip ROM. See above comment. > > If this is a P2020 you could use the on chip rom to copy u-boot to > L2SRAM and configure DDR via SPD - if you ever plan to change the > SODIMMs this could be very useful. > Yep, this is a P2020. I'll check the Freescale documentation. Hopefully it provides an example of how to configure the On-Chip ROM to use L2SRAM instead of DDR. I'll try and find a U-Boot port that configures DDR via SPD. I'm sure there are plenty, however any hints are welcome. :) Thanks for the input, Ira