Re: [PATCH V2 4/6] MIPS: lantiq: add basic support for FALC-ON

[Ralf Baechle <ralf@linux-mips.org>]

On Wed, Nov 16, 2011 at 03:28:16PM +0100, John Crispin wrote:

> +/* global register ranges */
> +extern __iomem void *ltq_ebu_membase;
> +extern __iomem void *ltq_sys1_membase;

extern void __iomem *ltq_ebu_membase;
extern void __iomem *ltq_sys1_membase;

> +#define ltq_ebu_w32(x, y)	ltq_w32((x), ltq_ebu_membase + (y))
> +#define ltq_ebu_r32(x)		ltq_r32(ltq_ebu_membase + (x))
> +#define ltq_ebu_w32_mask(clear, set, reg)   \
> +	ltq_ebu_w32((ltq_ebu_r32(reg) & ~(clear)) | (set), reg)
> +
> +#define ltq_sys1_w32(x, y)	ltq_w32((x), ltq_sys1_membase + (y))
> +#define ltq_sys1_r32(x)		ltq_r32(ltq_sys1_membase + (x))
> +#define ltq_sys1_w32_mask(clear, set, reg)   \
> +	ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
> +
> +/* gpio_request wrapper to help configure the pin */
> +extern int  ltq_gpio_request(unsigned int pin, unsigned int mux,
> +				unsigned int dir, const char *name);
> +extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux);
> +
> +/* to keep the irq code generic we need to define these to 0 as falcon
> +   has no EIU/EBU */
> +#define LTQ_EIU_BASE_ADDR	0
> +#define LTQ_EBU_PCC_ISTAT	0
> +
> +#define ltq_is_ar9()	0
> +#define ltq_is_vr9()	0

These days it is prefered to use inline functions rather than function-like
macro definitions such as these here.

Really, use inline functions unless you have a good reason not to.

  Ralf