From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: [PATCH] drm/i915: add multi-threaded forcewake support Date: Fri, 18 Nov 2011 11:36:32 -0800 Message-ID: <20111118113632.594717c8@jbarnes-desktop> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1971592602==" Return-path: Received: from oproxy8-pub.bluehost.com (oproxy8-pub.bluehost.com [69.89.22.20]) by gabe.freedesktop.org (Postfix) with SMTP id E4F209E832 for ; Fri, 18 Nov 2011 11:35:33 -0800 (PST) Received: from c-67-161-37-189.hsd1.ca.comcast.net ([67.161.37.189] helo=jbarnes-desktop) by box514.bluehost.com with esmtpsa (TLSv1:AES128-SHA:128) (Exim 4.76) (envelope-from ) id 1RRUDk-0001jF-SM for intel-gfx@lists.freedesktop.org; Fri, 18 Nov 2011 12:35:32 -0700 List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============1971592602== Content-Type: multipart/signed; micalg=PGP-SHA1; boundary="Sig_/ci9Xld7qzKVEU8naopyZ1Bq"; protocol="application/pgp-signature" --Sig_/ci9Xld7qzKVEU8naopyZ1Bq Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable On IVB C0+ with newer BIOSes, the forcewake handshake has changed. There's now a bitfield for different driver components to keep the GT powered on. On Linux, we centralize forcewake handling in one place, so we still just need a single bit, but we need to use the new registers if MT forcewake is enabled. This needs testing on affected machines. Please reply with your tested-by if you had problems after a BIOS upgrade and this patch fixes them. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.c | 35 ++++++++++++++++++++++++++++--= --- drivers/gpu/drm/i915/i915_drv.h | 13 ++++++++++- drivers/gpu/drm/i915/i915_reg.h | 4 +++ drivers/gpu/drm/i915/intel_display.c | 13 ++++++++++++ 4 files changed, 57 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_dr= v.c index 548e04b..629c591 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -327,7 +327,7 @@ void intel_detect_pch(struct drm_device *dev) } } =20 -static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) +void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) { int count; =20 @@ -343,6 +343,22 @@ static void __gen6_gt_force_wake_get(struct drm_i915_p= rivate *dev_priv) udelay(10); } =20 +void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) +{ + int count; + + count =3D 0; + while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1)) + udelay(10); + + I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<15) | 1); + POSTING_READ(FORCEWAKE_MT); + + count =3D 0; + while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) =3D=3D 0) + udelay(10); +} + /* * Generally this is called implicitly by the register read function. Howe= ver, * if some sequence requires the GT to not power down then this function s= hould @@ -355,15 +371,21 @@ void gen6_gt_force_wake_get(struct drm_i915_private *= dev_priv) =20 /* Forcewake is atomic in case we get in here without the lock */ if (atomic_add_return(1, &dev_priv->forcewake_count) =3D=3D 1) - __gen6_gt_force_wake_get(dev_priv); + dev_priv->display.force_wake_get(dev_priv); } =20 -static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) +void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) { I915_WRITE_NOTRACE(FORCEWAKE, 0); POSTING_READ(FORCEWAKE); } =20 +void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) +{ + I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<15) | 0); + POSTING_READ(FORCEWAKE_MT); +} + /* * see gen6_gt_force_wake_get() */ @@ -372,7 +394,7 @@ void gen6_gt_force_wake_put(struct drm_i915_private *de= v_priv) WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); =20 if (atomic_dec_and_test(&dev_priv->forcewake_count)) - __gen6_gt_force_wake_put(dev_priv); + dev_priv->display.force_wake_put(dev_priv); } =20 void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) @@ -902,8 +924,9 @@ MODULE_LICENSE("GPL and additional rights"); /* We give fast paths for the really cool registers */ #define NEEDS_FORCE_WAKE(dev_priv, reg) \ (((dev_priv)->info->gen >=3D 6) && \ - ((reg) < 0x40000) && \ - ((reg) !=3D FORCEWAKE)) + ((reg) < 0x40000) && \ + ((reg) !=3D FORCEWAKE) && \ + ((reg) !=3D ECOBUS)) =20 #define __i915_read(x, y) \ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_dr= v.h index 06a37f4..502ce9b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -107,6 +107,7 @@ struct opregion_header; struct opregion_acpi; struct opregion_swsci; struct opregion_asle; +struct drm_i915_private; =20 struct intel_opregion { struct opregion_header *header; @@ -218,6 +219,8 @@ struct drm_i915_display_funcs { struct drm_i915_gem_object *obj); int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, int x, int y); + void (*force_wake_get)(struct drm_i915_private *dev_priv); + void (*force_wake_put)(struct drm_i915_private *dev_priv); /* clock updates for mode set */ /* cursor updates */ /* render clock increase/decrease */ @@ -1307,6 +1310,11 @@ extern void gen6_set_rps(struct drm_device *dev, u8 = val); extern void intel_detect_pch(struct drm_device *dev); extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); =20 +extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); +extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv); +extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); +extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv); + /* overlay */ #ifdef CONFIG_DEBUG_FS extern struct intel_overlay_error_state *intel_overlay_capture_error_state= (struct drm_device *dev); @@ -1351,8 +1359,9 @@ void __gen6_gt_wait_for_fifo(struct drm_i915_private = *dev_priv); /* We give fast paths for the really cool registers */ #define NEEDS_FORCE_WAKE(dev_priv, reg) \ (((dev_priv)->info->gen >=3D 6) && \ - ((reg) < 0x40000) && \ - ((reg) !=3D FORCEWAKE)) + ((reg) < 0x40000) && \ + ((reg) !=3D FORCEWAKE) && \ + ((reg) !=3D ECOBUS)) =20 #define __i915_read(x, y) \ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_re= g.h index d486bab..1a8b6eb 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3567,7 +3567,11 @@ #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) =20 +#define ECOBUS 0xa180 +#define FORCEWAKE_MT_ENABLE (1<<5) #define FORCEWAKE 0xA18C +#define FORCEWAKE_MT 0xa188 /* multi-threaded */ +#define FORCEWAKE_MT_ACK 0x130040 #define FORCEWAKE_ACK 0x130090 =20 #define GT_FIFO_FREE_ENTRIES 0x120008 diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/in= tel_display.c index 3f165d3..1ab79ea 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8482,6 +8482,19 @@ static void intel_init_display(struct drm_device *de= v) =20 /* For FIFO watermark updates */ if (HAS_PCH_SPLIT(dev)) { + dev_priv->display.force_wake_get =3D __gen6_gt_force_wake_get; + dev_priv->display.force_wake_put =3D __gen6_gt_force_wake_put; + + /* IVB configs may use multi-threaded forcewake */ + if (IS_IVYBRIDGE(dev)) { + if (I915_READ(ECOBUS) & FORCEWAKE_MT_ENABLE) { + dev_priv->display.force_wake_get =3D + __gen6_gt_force_wake_mt_get; + dev_priv->display.force_wake_put =3D + __gen6_gt_force_wake_mt_put; + } + } + if (HAS_PCH_IBX(dev)) dev_priv->display.init_pch_clock_gating =3D ibx_init_clock_gating; else if (HAS_PCH_CPT(dev)) --=20 1.7.4.1 --Sig_/ci9Xld7qzKVEU8naopyZ1Bq Content-Type: application/pgp-signature; name=signature.asc Content-Disposition: attachment; filename=signature.asc -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iQIcBAEBAgAGBQJOxrPAAAoJEIEoDkX4Qk9hcm8P/R4Z9BI+xL9m8EVLZKrHRdVJ BalKtQYEyXdrxj7GW7BBn5j3F4HhpxaYczrDwZpl5rFJwoSPP2/uagY/pTJ/ff8a zOP7y5PcHK6cXl2LtfQ6GF0jhbsLzqtFt4/VoAvdsvfZN85jVZoFvGWaHR6wjqtR 8IHjdIMiZGDIue///pX+6FMa6WyhHs50jWvqtWsa2m1wADNwqKSeCx4efT0PIYIM sL/VF/7cMki8xhsNlgo6AxKCZtEfzJAnMEshamq0x6xcBbwhL0uptXeELJXkucH3 1yE2rKRF/5ZTiOhgCYPeI8F+QogYzK7h+eOCpoNHa0RH3YSEe/PjiB0TXWSk7Ii2 mKl0WUCPFvosXuXq3X6U/77bVIzWDXhzH60bDJkuzT4Dm5/AsVSr6s+jOD91NAsY i64zk18xIWxNKFSvYmcRjCxl3KrTKBR+Ir3gVNylGhIg5EH0IF6iQQuGCbFatgas DJaxlCG+XvZPl2oKKF2Lx4a0bPZrFtZcR4pE05+aLtGryW4Le2jq/ZCDLA8OSC5E Pg9dHCU2OXMPw5wdmt6A+PDT1ZgLuOWD41SYvvfsJj00iFo0H4HJaXzsZcnUjoEp r7IqaoN9V+X6eeUNT49/2U2ftlah7xEqM+dMqH5ewnwF5tadITCLauwUl5dINmvk CKg9b9lNzBNCgTH2YWLK =IRYa -----END PGP SIGNATURE----- --Sig_/ci9Xld7qzKVEU8naopyZ1Bq-- --===============1971592602== Content-Type: text/plain; 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