From: Daniel Vetter <daniel@ffwll.ch>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org,
Eugeni Dodonov <eugeni.dodonov@intel.com>
Subject: Re: [PATCH 2/2] drm/i915: add debugfs interface to control rc6 and rps
Date: Tue, 29 Nov 2011 15:12:50 +0100 [thread overview]
Message-ID: <20111129140843.GA5667@phenom.ffwll.local> (raw)
In-Reply-To: <e0d58a$2dba7q@orsmga002.jf.intel.com>
On Tue, Nov 29, 2011 at 01:05:03PM +0000, Chris Wilson wrote:
> On Tue, 29 Nov 2011 10:55:05 -0200, Eugeni Dodonov <eugeni.dodonov@intel.com> wrote:
> > This allows to enable/disable rps and rc6 from userspace. This is
> > necessary for to have predictable results from hardware counters, and also
> > to provide a finer granularity over power control from userspace.
>
> Reading registers and counters is handled with i915_forcewake_user. So
> the question is what benefit does htis give over module reload. It looks
> far riskier...
The observation architecture bspec says that we need to disable rc6,
otherwise we'll get garbage in the gpu perf counters. But imo I think this
should be handled in the kernel (we neeed to write tons of funny registers
to set things up anyway), at least for the time-based perf counter
sampling. For prototyping things with intel_reg_write disabling rc6 at
module load time seems sufficient to me.
-Daniel
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
next prev parent reply other threads:[~2011-11-29 14:11 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-11-29 12:55 [PATCH 1/2] drm/i915: enable deepest RC6 state Eugeni Dodonov
2011-11-29 12:55 ` [PATCH 2/2] drm/i915: add debugfs interface to control rc6 and rps Eugeni Dodonov
2011-11-29 13:05 ` Chris Wilson
2011-11-29 14:12 ` Daniel Vetter [this message]
2011-11-29 14:26 ` Eugeni Dodonov
2011-11-29 14:39 ` Chris Wilson
2011-11-29 13:01 ` [PATCH 1/2] drm/i915: enable deepest RC6 state Chris Wilson
2011-11-29 21:42 ` Ben Widawsky
2011-11-29 23:46 ` Eugeni Dodonov
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