diff for duplicates of <20111129164050.GC2829@localhost.localdomain> diff --git a/a/1.txt b/N1/1.txt index d3d1cec..c1aea4a 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -4,7 +4,7 @@ On Tue, Nov 29, 2011 at 03:11:13PM +0000, Pawel Moll wrote: > implementation of the DT machine support (this code is separate > from the current core tile code). > -> Signed-off-by: Pawel Moll <pawel.moll@arm.com> +> Signed-off-by: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org> > --- > arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 131 ++++++++++++++++++++++++++++ > arch/arm/boot/dts/vexpress-v2p-ca9.dts | 145 +++++++++++++++++++++++++++++++ @@ -50,30 +50,30 @@ On Tue, Nov 29, 2011 at 03:11:13PM +0000, Pawel Moll wrote: > + i2c1 = &v2m_i2c_pcie; > + }; > + -> + memory at 80000000 { +> + memory@80000000 { > + device_type = "memory"; > + reg = <0x80000000 0x40000000>; > + }; > + -> + hdlcd at 2a110000 { +> + hdlcd@2a110000 { > + compatible = "arm,hdlcd"; > + reg = <0x2a110000 0x1000>; > + interrupts = <0 85 4>; > + }; > + -> + memory-controller at 2a150000 { +> + memory-controller@2a150000 { > + compatible = "arm,pl341", "arm,primecell"; > + reg = <0x2a150000 0x1000>; > + }; > + -> + memory-controller at 2a190000 { +> + memory-controller@2a190000 { > + compatible = "arm,pl354", "arm,primecell"; > + reg = <0x2a190000 0x1000>; > + interrupts = <0 86 4>, > + <0 87 4>; > + }; > + -> + gic: interrupt-controller at 2c001000 { +> + gic: interrupt-controller@2c001000 { > + compatible = "arm,cortex-a9-gic"; > + #interrupt-cells = <3>; > + #address-cells = <0>; @@ -82,7 +82,7 @@ On Tue, Nov 29, 2011 at 03:11:13PM +0000, Pawel Moll wrote: > + <0x2c000100 0x100>; > + }; > + -> + L2: cache-controller at 2c0f0000 { +> + L2: cache-controller@2c0f0000 { > + compatible = "arm,pl310-cache"; > + reg = <0x2c0f0000 0x1000>; > + interrupts = <0 84 4>; @@ -187,43 +187,43 @@ On Tue, Nov 29, 2011 at 03:11:13PM +0000, Pawel Moll wrote: > + i2c1 = &v2m_i2c_pcie; > + }; > + -> + memory at 60000000 { +> + memory@60000000 { > + device_type = "memory"; > + reg = <0x60000000 0x40000000>; > + }; > + -> + clcd at 10020000 { +> + clcd@10020000 { > + compatible = "arm,pl111", "arm,primecell"; > + reg = <0x10020000 0x1000>; > + interrupts = <0 44 4>; > + }; > + -> + memory-controller at 100e0000 { +> + memory-controller@100e0000 { > + compatible = "arm,pl341", "arm,primecell"; > + reg = <0x100e0000 0x1000>; > + }; > + -> + memory-controller at 100e1000 { +> + memory-controller@100e1000 { > + compatible = "arm,pl354", "arm,primecell"; > + reg = <0x100e1000 0x1000>; > + interrupts = <0 45 4>, > + <0 46 4>; > + }; > + -> + timer at 100e4000 { +> + timer@100e4000 { > + compatible = "arm,sp804", "arm,primecell"; > + reg = <0x100e4000 0x1000>; > + interrupts = <0 48 4>, > + <0 49 4>; > + }; > + -> + watchdog at 100e5000 { +> + watchdog@100e5000 { > + compatible = "arm,sp805", "arm,primecell"; > + reg = <0x100e5000 0x1000>; > + interrupts = <0 51 4>; > + }; > + -> + gic: interrupt-controller at 1e001000 { +> + gic: interrupt-controller@1e001000 { > + compatible = "arm,cortex-a9-gic"; > + #interrupt-cells = <3>; > + #address-cells = <0>; @@ -232,7 +232,7 @@ On Tue, Nov 29, 2011 at 03:11:13PM +0000, Pawel Moll wrote: > + <0x1e000100 0x100>; > + }; > + -> + L2: cache-controller at 1e00a000 { +> + L2: cache-controller@1e00a000 { > + compatible = "arm,pl310-cache"; > + reg = <0x1e00a000 0x1000>; > + interrupts = <0 43 4>; diff --git a/a/content_digest b/N1/content_digest index 92ac63b..444dc19 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,9 +1,12 @@ "ref\01322579473-8804-1-git-send-email-pawel.moll@arm.com\0" "ref\01322579473-8804-6-git-send-email-pawel.moll@arm.com\0" - "From\0dave.martin@linaro.org (Dave Martin)\0" - "Subject\0[PATCH v3 5/5] ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4\0" + "ref\01322579473-8804-6-git-send-email-pawel.moll-5wv7dgnIgG8@public.gmane.org\0" + "From\0Dave Martin <dave.martin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\0" + "Subject\0Re: [PATCH v3 5/5] ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4\0" "Date\0Tue, 29 Nov 2011 16:40:50 +0000\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>\0" + "Cc\0devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org" + " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" "\00:1\0" "b\0" "On Tue, Nov 29, 2011 at 03:11:13PM +0000, Pawel Moll wrote:\n" @@ -12,7 +15,7 @@ "> implementation of the DT machine support (this code is separate\n" "> from the current core tile code).\n" "> \n" - "> Signed-off-by: Pawel Moll <pawel.moll@arm.com>\n" + "> Signed-off-by: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>\n" "> ---\n" "> arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 131 ++++++++++++++++++++++++++++\n" "> arch/arm/boot/dts/vexpress-v2p-ca9.dts | 145 +++++++++++++++++++++++++++++++\n" @@ -58,30 +61,30 @@ "> +\t\ti2c1 = &v2m_i2c_pcie;\n" "> +\t};\n" "> +\n" - "> +\tmemory at 80000000 {\n" + "> +\tmemory@80000000 {\n" "> +\t\tdevice_type = \"memory\";\n" "> +\t\treg = <0x80000000 0x40000000>;\n" "> +\t};\n" "> +\n" - "> +\thdlcd at 2a110000 {\n" + "> +\thdlcd@2a110000 {\n" "> +\t\tcompatible = \"arm,hdlcd\";\n" "> +\t\treg = <0x2a110000 0x1000>;\n" "> +\t\tinterrupts = <0 85 4>;\n" "> +\t};\n" "> +\n" - "> +\tmemory-controller at 2a150000 {\n" + "> +\tmemory-controller@2a150000 {\n" "> +\t\tcompatible = \"arm,pl341\", \"arm,primecell\";\n" "> +\t\treg = <0x2a150000 0x1000>;\n" "> +\t};\n" "> +\n" - "> +\tmemory-controller at 2a190000 {\n" + "> +\tmemory-controller@2a190000 {\n" "> +\t\tcompatible = \"arm,pl354\", \"arm,primecell\";\n" "> +\t\treg = <0x2a190000 0x1000>;\n" "> +\t\tinterrupts = <0 86 4>,\n" "> +\t\t\t <0 87 4>;\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller at 2c001000 {\n" + "> +\tgic: interrupt-controller@2c001000 {\n" "> +\t\tcompatible = \"arm,cortex-a9-gic\";\n" "> +\t\t#interrupt-cells = <3>;\n" "> +\t\t#address-cells = <0>;\n" @@ -90,7 +93,7 @@ "> +\t\t <0x2c000100 0x100>;\n" "> +\t};\n" "> +\n" - "> +\tL2: cache-controller at 2c0f0000 {\n" + "> +\tL2: cache-controller@2c0f0000 {\n" "> +\t\tcompatible = \"arm,pl310-cache\";\n" "> +\t\treg = <0x2c0f0000 0x1000>;\n" "> +\t\tinterrupts = <0 84 4>;\n" @@ -195,43 +198,43 @@ "> +\t\ti2c1 = &v2m_i2c_pcie;\n" "> +\t};\n" "> +\n" - "> +\tmemory at 60000000 {\n" + "> +\tmemory@60000000 {\n" "> +\t\tdevice_type = \"memory\";\n" "> +\t\treg = <0x60000000 0x40000000>;\n" "> +\t};\n" "> +\n" - "> +\tclcd at 10020000 {\n" + "> +\tclcd@10020000 {\n" "> +\t\tcompatible = \"arm,pl111\", \"arm,primecell\";\n" "> +\t\treg = <0x10020000 0x1000>;\n" "> +\t\tinterrupts = <0 44 4>;\n" "> +\t};\n" "> +\n" - "> +\tmemory-controller at 100e0000 {\n" + "> +\tmemory-controller@100e0000 {\n" "> +\t\tcompatible = \"arm,pl341\", \"arm,primecell\";\n" "> +\t\treg = <0x100e0000 0x1000>;\n" "> +\t};\n" "> +\n" - "> +\tmemory-controller at 100e1000 {\n" + "> +\tmemory-controller@100e1000 {\n" "> +\t\tcompatible = \"arm,pl354\", \"arm,primecell\";\n" "> +\t\treg = <0x100e1000 0x1000>;\n" "> +\t\tinterrupts = <0 45 4>,\n" "> +\t\t\t <0 46 4>;\n" "> +\t};\n" "> +\n" - "> +\ttimer at 100e4000 {\n" + "> +\ttimer@100e4000 {\n" "> +\t\tcompatible = \"arm,sp804\", \"arm,primecell\";\n" "> +\t\treg = <0x100e4000 0x1000>;\n" "> +\t\tinterrupts = <0 48 4>,\n" "> +\t\t\t <0 49 4>;\n" "> +\t};\n" "> +\n" - "> +\twatchdog at 100e5000 {\n" + "> +\twatchdog@100e5000 {\n" "> +\t\tcompatible = \"arm,sp805\", \"arm,primecell\";\n" "> +\t\treg = <0x100e5000 0x1000>;\n" "> +\t\tinterrupts = <0 51 4>;\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller at 1e001000 {\n" + "> +\tgic: interrupt-controller@1e001000 {\n" "> +\t\tcompatible = \"arm,cortex-a9-gic\";\n" "> +\t\t#interrupt-cells = <3>;\n" "> +\t\t#address-cells = <0>;\n" @@ -240,7 +243,7 @@ "> +\t\t <0x1e000100 0x100>;\n" "> +\t};\n" "> +\n" - "> +\tL2: cache-controller at 1e00a000 {\n" + "> +\tL2: cache-controller@1e00a000 {\n" "> +\t\tcompatible = \"arm,pl310-cache\";\n" "> +\t\treg = <0x1e00a000 0x1000>;\n" "> +\t\tinterrupts = <0 43 4>;\n" @@ -348,4 +351,4 @@ "Cheers\n" ---Dave -4198511ef7137ac6bde2619cf53033f068c0c5c7a093d3e38026375b0e0b0132 +7653156ad2a4e1f2f3c9c45135579a779063188f275bb1ffa632b73176ec0214
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