From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH] drm/i915: add multi-threaded forcewake support Date: Mon, 5 Dec 2011 14:42:56 -0800 Message-ID: <20111205144256.3c1e772e@jbarnes-desktop> References: <1865303E0DED764181A9D882DEF65FB6E64E55D55E@shsmsx502.ccr.corp.intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1273454171==" Return-path: Received: from oproxy9.bluehost.com (oproxy9.bluehost.com [69.89.24.6]) by gabe.freedesktop.org (Postfix) with SMTP id 5A9409E747 for ; Mon, 5 Dec 2011 14:40:25 -0800 (PST) In-Reply-To: <1865303E0DED764181A9D882DEF65FB6E64E55D55E@shsmsx502.ccr.corp.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: "Fang, XunX" Cc: "intel-gfx@lists.freedesktop.org" List-Id: intel-gfx@lists.freedesktop.org --===============1273454171== Content-Type: multipart/signed; micalg=PGP-SHA1; boundary="Sig_/ZADBnUXQ05cdCKrUR37jfyc"; protocol="application/pgp-signature" --Sig_/ZADBnUXQ05cdCKrUR37jfyc Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable On Mon, 21 Nov 2011 14:55:51 +0800 "Fang, XunX" wrote: > void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) > @@ -902,8 +924,9 @@ MODULE_LICENSE("GPL and additional rights"); > /* We give fast paths for the really cool registers */ > #define NEEDS_FORCE_WAKE(dev_priv, reg) \ > (((dev_priv)->info->gen >=3D 6) && \ > - ((reg) < 0x40000) && \ > - ((reg) !=3D FORCEWAKE)) > + ((reg) < 0x40000) && \ > + ((reg) !=3D FORCEWAKE) && \ > + ((reg) !=3D ECOBUS)) Both instances of this macro need to drop the ECOBUS check now that we know it's in the GT power well. > =20 > #define __i915_read(x, y) \ > u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_= drv.h > index 4a9c1b9..8ba88cf 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -107,6 +107,7 @@ struct opregion_header; > struct opregion_acpi; > struct opregion_swsci; > struct opregion_asle; > +struct drm_i915_private; > =20 > struct intel_opregion { > struct opregion_header *header; > @@ -221,6 +222,8 @@ struct drm_i915_display_funcs { > struct drm_i915_gem_object *obj); > int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, > int x, int y); > + void (*force_wake_get)(struct drm_i915_private *dev_priv); > + void (*force_wake_put)(struct drm_i915_private *dev_priv); > /* clock updates for mode set */ > /* cursor updates */ > /* render clock increase/decrease */ > @@ -1308,6 +1311,11 @@ extern void gen6_set_rps(struct drm_device *dev, u= 8 val); > extern void intel_detect_pch(struct drm_device *dev); > extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); > =20 > +extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); > +extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_pri= v); > +extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); > +extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_pri= v); > + > /* overlay */ > #ifdef CONFIG_DEBUG_FS > extern struct intel_overlay_error_state *intel_overlay_capture_error_sta= te(struct drm_device *dev); > @@ -1352,8 +1360,9 @@ void __gen6_gt_wait_for_fifo(struct drm_i915_privat= e *dev_priv); > /* We give fast paths for the really cool registers */ > #define NEEDS_FORCE_WAKE(dev_priv, reg) \ > (((dev_priv)->info->gen >=3D 6) && \ > - ((reg) < 0x40000) && \ > - ((reg) !=3D FORCEWAKE)) > + ((reg) < 0x40000) && \ > + ((reg) !=3D FORCEWAKE) && \ > + ((reg) !=3D ECOBUS)) > =20 > #define __i915_read(x, y) \ > u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index b080cc8..8990057 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3449,6 +3449,10 @@ > =20 > #define FORCEWAKE 0xA18C > #define FORCEWAKE_ACK 0x130090 > +#define FORCEWAKE_MT 0xa188 /* multi-threaded */ > +#define FORCEWAKE_MT_ACK 0x130040 > +#define ECOBUS 0xa180 > +#define FORCEWAKE_MT_ENABLE (1<<5) > =20 > #define GT_FIFO_FREE_ENTRIES 0x120008 > #define GT_FIFO_NUM_RESERVED_ENTRIES 20 > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index e77a863..633c693 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -8491,6 +8491,28 @@ static void intel_init_display(struct drm_device *= dev) > =20 > /* For FIFO watermark updates */ > if (HAS_PCH_SPLIT(dev)) { > + dev_priv->display.force_wake_get =3D __gen6_gt_force_wake_get; > + dev_priv->display.force_wake_put =3D __gen6_gt_force_wake_put; > + > + /* IVB configs may use multi-threaded forcewake */ > + if (IS_IVYBRIDGE(dev)) { > + u32 ecobus; > + > + mutex_lock(&dev->struct_mutex); > + __gen6_gt_force_wake_mt_get(dev_priv); > + ecobus =3D I915_READ(ECOBUS); > + __gen6_gt_force_wake_mt_put(dev_priv); > + mutex_unlock(&dev->struct_mutex); > + > + if (ecobus & FORCEWAKE_MT_ENABLE) { > + DRM_DEBUG_KMS("Using MT version of forcewake\n"); > + dev_priv->display.force_wake_get =3D > + __gen6_gt_force_wake_mt_get; > + dev_priv->display.force_wake_put =3D > + __gen6_gt_force_wake_mt_put; > + } > + } I think we need: I915_WRITE(GEN6_RC_STATE, 0); I915_WRITE(GEN6_RC_SLEEP, 0); above the force_wake_get here. And as long as it comes before enable_rps, we'll properly re-enable RC6 and turbo later. Anyone want to test with the suggested changes and report back? Thanks, --=20 Jesse Barnes, Intel Open Source Technology Center --Sig_/ZADBnUXQ05cdCKrUR37jfyc Content-Type: application/pgp-signature; name=signature.asc Content-Disposition: attachment; filename=signature.asc -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iQIcBAEBAgAGBQJO3UjwAAoJEIEoDkX4Qk9hWMUQALp0y0pQ70PYWK3vLag31Wht xVx8d+FKIy4Fd5xVzm9LaGNvd78Ab3s750T39yI4lsGL48Cke/HPd4VBsHnZ3dFV Rcn4f62gSzRNwwdPG2jTlgdgeL77MdIELmY94oxxz+T7vF+WWeTCFCSTpBTnchcH Y4gza3KEIc4uLcLREH7SLgKbeH9EF07pFLBG/mreBzbW9a2WwUipIwmNNqtb0Mqj 6E4zsnvgWOdW99KIog+Gqswtear1JvjzuPg2Ryo4kszNt7PgEUZR3PGmkrS4sPCW KMqFG8f7uX/A/lJ/UmVINJ7uvnR4cNBgBtooWyGG5NaCWb7Tk4bcxG3DVeUzmdxP 9ghHynkSOnmYF5H/NxC7QiL1ssat+W5yT7Y4hM+bhSZoDnhA9O0wNWEWJB3s9TIV 89T9XV4zjV+pat14aJuXR7K4RfLZwosT/mv2VqjrJD0c1yYwq44gwMXK3x1dznR+ dwlw0BGBXnGo8bwYNBTIxBHTmMgWy+3yzNrVG4pm44Z8cjDKMJmGb/hta4x6GIyt eyoR70mAL7GEX1lpmbJOdA666+mYpU68kml9v5zJLWCd3iBiUAyzeEoviOyA24rv u2zEDJ4lzOU7s+NaQgnYukfnLvdjeiCUlHUqdQiaawavTmZYxutvlShqXYd8Y1bH XEuiB1VUY9l2+Zgir4Fx =b6/O -----END PGP SIGNATURE----- --Sig_/ZADBnUXQ05cdCKrUR37jfyc-- --===============1273454171== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============1273454171==--