From: Ralf Baechle <ralf@linux-mips.org>
To: David Daney <ddaney.cavm@gmail.com>
Cc: linux-mips@linux-mips.org, David Daney <david.daney@cavium.com>
Subject: Re: [PATCH] MIPS: Octeon: Don't increase PCIe payload sizes.
Date: Thu, 8 Dec 2011 12:35:09 +0000 [thread overview]
Message-ID: <20111208123509.GA10113@linux-mips.org> (raw)
In-Reply-To: <1322761877-30221-1-git-send-email-ddaney.cavm@gmail.com>
On Thu, Dec 01, 2011 at 09:51:17AM -0800, David Daney wrote:
> The existing code breaks devices that are capable of large PCIe
> transfers (Silicon Image SATA controllers for example). We don't have
> code to properly determine the maximum payload size on a per-bus
> basis, so the easiest thing to do is just have all devices use the
> default (128).
Folded into 53ba9ae0 [MIPS: Octeon: Update PCI Latency timer, PCIe payload,
and PCIe max read to allow larger transactions].
Thanks,
Ralf
prev parent reply other threads:[~2011-12-08 12:35 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-12-01 17:51 [PATCH] MIPS: Octeon: Don't increase PCIe payload sizes David Daney
2011-12-08 12:35 ` Ralf Baechle [this message]
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