From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:56899) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RZ2n3-0005h5-I7 for qemu-devel@nongnu.org; Fri, 09 Dec 2011 10:55:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RZ2my-00089t-DC for qemu-devel@nongnu.org; Fri, 09 Dec 2011 10:55:13 -0500 Received: from relay1.mentorg.com ([192.94.38.131]:37337) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RZ2my-00087w-8u for qemu-devel@nongnu.org; Fri, 09 Dec 2011 10:55:08 -0500 From: Paul Brook Date: Fri, 9 Dec 2011 15:55:01 +0000 References: <1323437682-28792-1-git-send-email-e.voevodin@samsung.com> <1323437682-28792-9-git-send-email-e.voevodin@samsung.com> In-Reply-To: <1323437682-28792-9-git-send-email-e.voevodin@samsung.com> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-6" Content-Transfer-Encoding: 7bit Message-Id: <201112091555.02533.paul@codesourcery.com> Subject: Re: [Qemu-devel] [PATCH 08/15] hw/arm_gic.c: lower IRQ only on changing of enable bit. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: m.kozlov@samsung.com, d.solodkiy@samsung.com, Evgeny Voevodin > In previous version IRQ was lowered every time if enable bits were > not set. If platform has splitted IRQ source to pass IRQ to two > identical GICs simultaneously in first of which IRQ passing is > enabled but in second is disabled, handling IRQ by second GIC would > lower IRQ previously raised by first GIC. > Linux kernel v3.0 faces this problem. > The problem is avoided if IRQ is only lowered as result of > transitioning enable bits to zeroes. This is almost certainly wrong. IRQ lines are state based, not event based. Re-asserting an existing level should always be a no-op. My guess is your real bug it that your IRQ wiring is broken, and you have multiple outputs connected to a single input. Don't do that. Ever. If you need to connent multiple output pins to a single input pin then you need an explicit device (e.g. an or gate) in between. Paul