From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:41180) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rm4ub-0000bV-Qa for qemu-devel@nongnu.org; Sat, 14 Jan 2012 09:48:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rm4ua-0004zh-Lk for qemu-devel@nongnu.org; Sat, 14 Jan 2012 09:48:53 -0500 Received: from hall.aurel32.net ([88.191.126.93]:40426) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rm4ua-0004zc-H9 for qemu-devel@nongnu.org; Sat, 14 Jan 2012 09:48:52 -0500 Date: Sat, 14 Jan 2012 15:48:50 +0100 From: Aurelien Jarno Message-ID: <20120114144850.GD711@hall.aurel32.net> References: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: Sender: Aurelien Jarno Subject: Re: [Qemu-devel] throwing away translated code on CPU reset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: QEMU Developers , Alexander Graf On Thu, Jan 12, 2012 at 02:00:38PM +0000, Peter Maydell wrote: > When doing TCG code translation, the target-foo translate.c > code is allowed to bake assumptions into the generated code from > the current values of various fields in the CPUState. This then > imposes the requirement that if the field is changed then tb_flush > must be called to throw away the now-incorrect generated code. > > However, cpu_reset() changes (unsurprisingly) lots of fields in > the CPUState, but it doesn't call tb_flush()... > > So should cpu_reset() implementations be changed to call tb_flush() > as well as tlb_flush(), or is this supposed to work in some other > way? We use the hflags to determine in which conditions the cached code has been generated, so that we only used the cache code if the CPU is in the same mode. I therefore don't think there is a real need to flush the cached code. What should be ensured on the other hand, is that hflag is correctly updated during or after the reset. This is the case for at least PowerPC and MIPS. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net