From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 1/2] drm/i915: Remove the MI_FLUSH_ENABLE setting. Date: Thu, 19 Jan 2012 19:53:29 +0100 Message-ID: <20120119185329.GJ3779@phenom.ffwll.local> References: <1326999006-15100-1-git-send-email-eric@anholt.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-we0-f177.google.com (mail-we0-f177.google.com [74.125.82.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 2AF349E853 for ; Thu, 19 Jan 2012 10:53:31 -0800 (PST) Received: by werm13 with SMTP id m13so287455wer.36 for ; Thu, 19 Jan 2012 10:53:31 -0800 (PST) Content-Disposition: inline In-Reply-To: <1326999006-15100-1-git-send-email-eric@anholt.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Eric Anholt Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Jan 19, 2012 at 10:50:05AM -0800, Eric Anholt wrote: > We have always been using the wrong bit -- it's bit 12. However, the > bit also doesn't do anything -- hardware has always accepted the > MI_FLUSH command even when it was specced not to. > > Given that there is only one MI_FLUSH emitted in all of the driver > stack on gen6+ (in i965_video.c of the 2d driver, and it should be > using other code to do its flush instead), just remove the MI_FLUSH > enable instead of trying to fix it. > > Signed-off-by: Eric Anholt The other thing is that I've just tested the bit11 | bit12 patch from Ben on my ivb, and it resulted in a nice system death, like setting bit12 on snb. So whoever wrote that piece of bspec didn't talk with whomever implemented it ... Reviewed-by: Daniel Vetter -- Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48