From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 2/2] drm/i915: Correct the bit number for
 the MI_FLUSH_ENABLE.
Date: Wed, 25 Jan 2012 11:41:16 +0100
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To: Chris Wilson <chris@chris-wilson.co.uk>
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On Wed, Jan 25, 2012 at 09:57:58AM +0000, Chris Wilson wrote:
> On Tue, 24 Jan 2012 18:55:53 -0800, Eric Anholt <eric@anholt.net> wrote:
> > On Sat, 21 Jan 2012 17:36:13 +0100, Daniel Vetter <daniel@ffwll.ch> wrote:
> > > On Thu, Jan 19, 2012 at 10:50:06AM -0800, Eric Anholt wrote:
> > > > Older specs claimed this was bit 11, but newer specs and the actual
> > > > simulator code say it was bit 12.  Regardless, we don't use MI_FLUSH,
> > > > or try to enable it any more.
> > > > 
> > > > Signed-off-by: Eric Anholt <eric@anholt.net>
> > > 
> > > I'd like to amend this with the following (on this patch instead of the
> > > other, so that ppl actually can find it with git blame):
> > > 
> > > "Furthermore actually setting bit12 results in gpu hangs both on snb and
> > > ivb. Ben Widawsky discovered a ppt that claims that both bit12 and bit11
> > > must be set, but that doesn't help either. And last but not least,
> > > MI_FLUSH seems to work regardless of the setting of these bits."
> > 
> > I haven't seen bit12 hanging snb/ivb -- I only knew of it hanging ilk
> > (since it doesn't exist there).  On my snb, running xvideo so that
> > MI_FLUSHes are generated by the userland (I think -- I haven't caught
> > them in cat i915_batchbuffers | intel_dump_decode -), with
> > intel_reg_read 0x209c saying 0x1240, things are going fine.  Also with
> > 0x209c saying 0x240 (the result of this patch).
> 
> The SNB Xv path, that is the code called by Gen6DisplayVideoTexture, 
> never used MI_FLUSH.

Ok, I've quickly tested this with intel_reg_write and installing older
userspace. Doesn't seem to blow up.
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48