From: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>,
benh <benh@kernel.crashing.org>, davem <davem@davemloft.net>,
"H. Peter Anvin" <hpa@zytor.com>,
Linux-Arch <linux-arch@vger.kernel.org>,
Ingo Molnar <mingo@elte.hu>, dhowells <dhowells@redhat.com>
Subject: Re: on memory barriers and cachelines
Date: Wed, 1 Feb 2012 06:22:19 -0800 [thread overview]
Message-ID: <20120201142218.GF2488@linux.vnet.ibm.com> (raw)
In-Reply-To: <1328088838.2760.21.camel@laptop>
On Wed, Feb 01, 2012 at 10:33:58AM +0100, Peter Zijlstra wrote:
> Hi all,
>
> So I was talking to Paul yesterday and he mentioned how the SRCU sync
> primitive has to use extra synchronize_sched() calls in order to avoid
> smp_rmb() calls in the srcu_read_{un,}lock() calls.
>
> Now memory barriers are usually explained as observable order between
> two (or more) unrelated variables, as Documentation/memory-barriers.txt
> does in great detail.
>
> What I couldn't find in there though, is what happens when both
> variables are on the same cacheline. The "The effects of the CPU cache"
> and "Cache coherency" sections are closest but leave me wanting on this
> point.
>
> Can we get some implicit behaviour from being on the same cacheline? Or
> can this memory access queue still totally wreck the game?
I don't know of any guarantees in this area, but am checking with
hardware architects for a couple of architectures.
Thanx, Paul
next prev parent reply other threads:[~2012-02-01 14:22 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-02-01 9:33 on memory barriers and cachelines Peter Zijlstra
2012-02-01 14:22 ` Paul E. McKenney [this message]
2012-02-10 2:51 ` Jamie Lokier
2012-02-10 16:32 ` Paul E. McKenney
2012-02-10 18:13 ` Peter Zijlstra
2012-02-10 18:47 ` Paul E. McKenney
2012-02-01 17:17 ` Linus Torvalds
2012-02-01 17:29 ` Peter Zijlstra
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