From: Tim Deegan <tim@xen.org>
To: Andres Lagar-Cavilla <andres@lagarcavilla.org>
Cc: olaf@aepfle.de, xen-devel@lists.xensource.com,
Wei Wang <wei.wang2@amd.com>,
keir.xen@gmail.com, jbeulich@suse.com, adin@gridcentric.ca
Subject: Re: RFC: AMD support for paging
Date: Wed, 15 Feb 2012 17:34:35 +0000 [thread overview]
Message-ID: <20120215173435.GD28101@ocelot.phlegethon.org> (raw)
In-Reply-To: <542008e21423a7c8aab407319824634e.squirrel@webmail.lagarcavilla.org>
At 09:09 -0800 on 15 Feb (1329296951), Andres Lagar-Cavilla wrote:
> That's basically my thinking, these are mutually exclusive conditions. And
> I'm curious as to whether that is causing the triple fault that's killing
> my domains.
I doubt it - at least not directly. Have you passed through a PCI[e]
card to them?
> You seem to imply that p2m+IOMMU unification is turned on by
> default -- that would crash PoD domains on AMD, wouldn't it?
Only PoD + passthrough, if you happened to DMA to a non-populated
address. But the same is true on Intel (though not all Intel h/w has
compatible EPT and VT-D tables).
Cheers,
Tim.
next prev parent reply other threads:[~2012-02-15 17:34 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-02-14 19:05 RFC: AMD support for paging Andres Lagar-Cavilla
2012-02-14 19:22 ` Olaf Hering
2012-02-14 19:35 ` Andres Lagar-Cavilla
2012-02-14 21:26 ` Olaf Hering
2012-02-14 21:33 ` Andres Lagar-Cavilla
2012-02-14 21:43 ` Olaf Hering
2012-02-15 9:18 ` Olaf Hering
2012-02-15 14:59 ` Andres Lagar-Cavilla
2012-02-15 12:09 ` Wei Wang
2012-02-15 15:14 ` Andres Lagar-Cavilla
2012-02-15 15:33 ` Wei Wang
2012-02-15 16:06 ` Andres Lagar-Cavilla
2012-02-15 17:02 ` Tim Deegan
2012-02-15 17:09 ` Andres Lagar-Cavilla
2012-02-15 17:34 ` Tim Deegan [this message]
2012-02-16 15:47 ` Wei Wang
2012-02-16 10:17 ` Wei Wang
2012-02-16 14:36 ` Andres Lagar-Cavilla
2012-02-16 2:31 ` Hongkaixing
2012-02-16 5:19 ` Andres Lagar-Cavilla
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