From: srinidhi.kasagar@stericsson.com (Srinidhi Kasagar)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/2] mach-ux500: cache operations are atomic on PL310
Date: Wed, 7 Mar 2012 15:02:42 +0530 [thread overview]
Message-ID: <20120307093240.GA21265@bnru02> (raw)
In-Reply-To: <20120117133428.GB11581@mudshark.cambridge.arm.com>
On Tue, Jan 17, 2012 at 14:34:28 +0100, Will Deacon wrote:
> On Tue, Jan 17, 2012 at 11:27:43AM +0000, Srinidhi KASAGAR wrote:
> > On Tue, Jan 17, 2012 at 11:30:23 +0100, Will Deacon wrote:
> > > On Tue, Jan 17, 2012 at 06:22:26AM +0000, Srinidhi KASAGAR wrote:
> > > >
> > > > Yes, we boot with L2 enabled.
> > >
> > > Interesting. I'm surprised you don't have problems with stale data on the
> > > D-side after the decompressor. Maybe you're lucky with the mappings being no
> > > write allocate.
> >
> > Actually the pre bootloader makes sure that L2 is clean before relinquishing
> > the control to kernel decompressor.
>
> I was thinking more of the decompressor populating the L2 and not flushing
> it.
Perhaps, we are lucky because we lock down l2 in bootloader?
srinidhi
prev parent reply other threads:[~2012-03-07 9:32 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-01-12 5:37 [PATCH 1/2] mach-ux500: cache operations are atomic on PL310 Srinidhi KASAGAR
2012-01-12 5:37 ` [PATCH 2/2] mach-ux500: enable ARM errata 764369 Srinidhi KASAGAR
2012-01-13 18:14 ` [PATCH 1/2] mach-ux500: cache operations are atomic on PL310 Will Deacon
2012-01-16 11:05 ` Srinidhi KASAGAR
2012-01-16 14:50 ` Will Deacon
2012-01-17 6:22 ` Srinidhi KASAGAR
2012-01-17 10:30 ` Will Deacon
2012-01-17 11:27 ` Srinidhi KASAGAR
2012-01-17 13:34 ` Will Deacon
2012-01-18 12:06 ` Linus Walleij
2012-03-07 9:32 ` Srinidhi Kasagar [this message]
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