From: Michael Roth <mdroth@linux.vnet.ibm.com>
To: Juan Quintela <quintela@redhat.com>
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 16/36] vmstate: port sparc cpu
Date: Wed, 21 Mar 2012 17:46:36 -0500 [thread overview]
Message-ID: <20120321224636.GF18965@illuin> (raw)
In-Reply-To: <d20c42a072ff6000adb35de883f1d139cb6e0317.1332197811.git.quintela@redhat.com>
On Mon, Mar 19, 2012 at 11:57:44PM +0100, Juan Quintela wrote:
> Signed-off-by: Juan Quintela <quintela@redhat.com>
> ---
> hw/sun4u.c | 20 --
> target-sparc/cpu.h | 9 +-
> target-sparc/machine.c | 474 ++++++++++++++++++++++++++++--------------------
> 3 files changed, 283 insertions(+), 220 deletions(-)
>
> diff --git a/hw/sun4u.c b/hw/sun4u.c
> index 237e20c..c36861c 100644
> --- a/hw/sun4u.c
> +++ b/hw/sun4u.c
> @@ -330,26 +330,6 @@ typedef struct ResetData {
> uint64_t prom_addr;
> } ResetData;
>
> -void cpu_put_timer(QEMUFile *f, CPUTimer *s)
> -{
> - qemu_put_be32s(f, &s->frequency);
> - qemu_put_be32s(f, &s->disabled);
> - qemu_put_be64s(f, &s->disabled_mask);
> - qemu_put_sbe64s(f, &s->clock_offset);
> -
> - qemu_put_timer(f, s->qtimer);
> -}
> -
> -void cpu_get_timer(QEMUFile *f, CPUTimer *s)
> -{
> - qemu_get_be32s(f, &s->frequency);
> - qemu_get_be32s(f, &s->disabled);
> - qemu_get_be64s(f, &s->disabled_mask);
> - qemu_get_sbe64s(f, &s->clock_offset);
> -
> - qemu_get_timer(f, s->qtimer);
> -}
> -
> static CPUTimer* cpu_timer_create(const char* name, CPUSPARCState *env,
> QEMUBHFunc *cb, uint32_t frequency,
> uint64_t disabled_mask)
> diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
> index 1025752..ba9b833 100644
> --- a/target-sparc/cpu.h
> +++ b/target-sparc/cpu.h
> @@ -374,10 +374,6 @@ struct CPUTimer
>
> typedef struct CPUTimer CPUTimer;
>
> -struct QEMUFile;
> -void cpu_put_timer(struct QEMUFile *f, CPUTimer *s);
> -void cpu_get_timer(struct QEMUFile *f, CPUTimer *s);
> -
> typedef struct CPUSPARCState CPUSPARCState;
>
> struct CPUSPARCState {
> @@ -509,6 +505,9 @@ struct CPUSPARCState {
>
> /* Leon3 cache control */
> uint32_t cache_control;
> +
> + /* Fields needed as intermediate for vmstate */
> + uint32_t psr_vmstate;
> };
>
> #ifndef NO_CPU_IO_DEFS
> @@ -596,8 +595,6 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
> #define cpu_signal_handler cpu_sparc_signal_handler
> #define cpu_list sparc_cpu_list
>
> -#define CPU_SAVE_VERSION 7
> -
> /* MMU modes definitions */
> #if defined (TARGET_SPARC64)
> #define MMU_USER_IDX 0
> diff --git a/target-sparc/machine.c b/target-sparc/machine.c
> index eb4d87f..801ec55 100644
> --- a/target-sparc/machine.c
> +++ b/target-sparc/machine.c
> @@ -4,214 +4,300 @@
>
> #include "cpu.h"
>
> -void cpu_save(QEMUFile *f, void *opaque)
> -{
> - CPUSPARCState *env = opaque;
> - int i;
> - uint32_t tmp;
> -
> - // if env->cwp == env->nwindows - 1, this will set the ins of the last
> - // window as the outs of the first window
> - cpu_set_cwp(env, env->cwp);
> +static const VMStateDescription vmstate_cpu_timer = {
> + .name = "cpu_timer",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .minimum_version_id_old = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT32(frequency, CPUTimer),
> + VMSTATE_UINT32(disabled, CPUTimer),
> + VMSTATE_UINT64(disabled_mask, CPUTimer),
> + VMSTATE_INT64(clock_offset, CPUTimer),
> + VMSTATE_TIMER(qtimer, CPUTimer),
> + VMSTATE_END_OF_LIST()
> + }
> +};
>
> - for(i = 0; i < 8; i++)
> - qemu_put_betls(f, &env->gregs[i]);
> - qemu_put_be32s(f, &env->nwindows);
> - for(i = 0; i < env->nwindows * 16; i++)
> - qemu_put_betls(f, &env->regbase[i]);
> +#define VMSTATE_CPU_TIMER(_f, _s) \
> + VMSTATE_STRUCT_POINTER(_f, _s, vmstate_cpu_timer, CPUTimer *)
>
> - /* FPU */
> - for (i = 0; i < TARGET_DPREGS; i++) {
> - qemu_put_be32(f, env->fpr[i].l.upper);
> - qemu_put_be32(f, env->fpr[i].l.lower);
> +#if defined(TARGET_SPARC64)
> +static const VMStateDescription vmstate_trap_state = {
> + .name = "trap_state",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .minimum_version_id_old = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT64(tpc, trap_state),
> + VMSTATE_UINT64(tnpc, trap_state),
> + VMSTATE_UINT64(tstate, trap_state),
> + VMSTATE_UINT32(tt, trap_state),
> + VMSTATE_END_OF_LIST()
> }
> +};
>
> - qemu_put_betls(f, &env->pc);
> - qemu_put_betls(f, &env->npc);
> - qemu_put_betls(f, &env->y);
> - tmp = cpu_get_psr(env);
> - qemu_put_be32(f, tmp);
> - qemu_put_betls(f, &env->fsr);
> - qemu_put_betls(f, &env->tbr);
> - tmp = env->interrupt_index;
> - qemu_put_be32(f, tmp);
> - qemu_put_be32s(f, &env->pil_in);
> -#ifndef TARGET_SPARC64
> - qemu_put_be32s(f, &env->wim);
> - /* MMU */
> - for (i = 0; i < 32; i++)
> - qemu_put_be32s(f, &env->mmuregs[i]);
> - for (i = 0; i < 4; i++) {
> - qemu_put_be64s(f, &env->mxccdata[i]);
> - }
> - for (i = 0; i < 8; i++) {
> - qemu_put_be64s(f, &env->mxccregs[i]);
> - }
> - qemu_put_be32s(f, &env->mmubpctrv);
> - qemu_put_be32s(f, &env->mmubpctrc);
> - qemu_put_be32s(f, &env->mmubpctrs);
> - qemu_put_be64s(f, &env->mmubpaction);
> - for (i = 0; i < 4; i++) {
> - qemu_put_be64s(f, &env->mmubpregs[i]);
> +static const VMStateDescription vmstate_tlb_entry = {
> + .name = "tlb_entry",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .minimum_version_id_old = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT64(tag, SparcTLBEntry),
> + VMSTATE_UINT64(tte, SparcTLBEntry),
> + VMSTATE_END_OF_LIST()
> }
> -#else
> - qemu_put_be64s(f, &env->lsu);
> - for (i = 0; i < 16; i++) {
> - qemu_put_be64s(f, &env->immuregs[i]);
> - qemu_put_be64s(f, &env->dmmuregs[i]);
> - }
> - for (i = 0; i < 64; i++) {
> - qemu_put_be64s(f, &env->itlb[i].tag);
> - qemu_put_be64s(f, &env->itlb[i].tte);
> - qemu_put_be64s(f, &env->dtlb[i].tag);
> - qemu_put_be64s(f, &env->dtlb[i].tte);
> - }
> - qemu_put_be32s(f, &env->mmu_version);
> - for (i = 0; i < MAXTL_MAX; i++) {
> - qemu_put_be64s(f, &env->ts[i].tpc);
> - qemu_put_be64s(f, &env->ts[i].tnpc);
> - qemu_put_be64s(f, &env->ts[i].tstate);
> - qemu_put_be32s(f, &env->ts[i].tt);
> - }
> - qemu_put_be32s(f, &env->xcc);
> - qemu_put_be32s(f, &env->asi);
> - qemu_put_be32s(f, &env->pstate);
> - qemu_put_be32s(f, &env->tl);
> - qemu_put_be32s(f, &env->cansave);
> - qemu_put_be32s(f, &env->canrestore);
> - qemu_put_be32s(f, &env->otherwin);
> - qemu_put_be32s(f, &env->wstate);
> - qemu_put_be32s(f, &env->cleanwin);
> - for (i = 0; i < 8; i++)
> - qemu_put_be64s(f, &env->agregs[i]);
> - for (i = 0; i < 8; i++)
> - qemu_put_be64s(f, &env->bgregs[i]);
> - for (i = 0; i < 8; i++)
> - qemu_put_be64s(f, &env->igregs[i]);
> - for (i = 0; i < 8; i++)
> - qemu_put_be64s(f, &env->mgregs[i]);
> - qemu_put_be64s(f, &env->fprs);
> - qemu_put_be64s(f, &env->tick_cmpr);
> - qemu_put_be64s(f, &env->stick_cmpr);
> - cpu_put_timer(f, env->tick);
> - cpu_put_timer(f, env->stick);
> - qemu_put_be64s(f, &env->gsr);
> - qemu_put_be32s(f, &env->gl);
> - qemu_put_be64s(f, &env->hpstate);
> - for (i = 0; i < MAXTL_MAX; i++)
> - qemu_put_be64s(f, &env->htstate[i]);
> - qemu_put_be64s(f, &env->hintp);
> - qemu_put_be64s(f, &env->htba);
> - qemu_put_be64s(f, &env->hver);
> - qemu_put_be64s(f, &env->hstick_cmpr);
> - qemu_put_be64s(f, &env->ssr);
> - cpu_put_timer(f, env->hstick);
> +};
> #endif
> -}
>
> -int cpu_load(QEMUFile *f, void *opaque, int version_id)
> +static void cpu_pre_save(void *opaque)
> {
> CPUSPARCState *env = opaque;
> - int i;
> - uint32_t tmp;
>
> - if (version_id < 6)
> - return -EINVAL;
> - for(i = 0; i < 8; i++)
> - qemu_get_betls(f, &env->gregs[i]);
> - qemu_get_be32s(f, &env->nwindows);
> - for(i = 0; i < env->nwindows * 16; i++)
> - qemu_get_betls(f, &env->regbase[i]);
> + /* if env->cwp == env->nwindows - 1, this will set the ins of the last
> + * window as the outs of the first window
> + */
> + cpu_set_cwp(env, env->cwp);
> + env->psr_vmstate = cpu_get_psr(env);
> +}
>
> - /* FPU */
> - for (i = 0; i < TARGET_DPREGS; i++) {
> - env->fpr[i].l.upper = qemu_get_be32(f);
> - env->fpr[i].l.lower = qemu_get_be32(f);
> - }
> +static int cpu_post_load(void *opaque, int version_id)
> +{
> + CPUSPARCState *env = opaque;
>
> - qemu_get_betls(f, &env->pc);
> - qemu_get_betls(f, &env->npc);
> - qemu_get_betls(f, &env->y);
> - tmp = qemu_get_be32(f);
> env->cwp = 0; /* needed to ensure that the wrapping registers are
> correctly updated */
> - cpu_put_psr(env, tmp);
> - qemu_get_betls(f, &env->fsr);
> - qemu_get_betls(f, &env->tbr);
> - tmp = qemu_get_be32(f);
> - env->interrupt_index = tmp;
> - qemu_get_be32s(f, &env->pil_in);
> -#ifndef TARGET_SPARC64
> - qemu_get_be32s(f, &env->wim);
> - /* MMU */
> - for (i = 0; i < 32; i++)
> - qemu_get_be32s(f, &env->mmuregs[i]);
> - for (i = 0; i < 4; i++) {
> - qemu_get_be64s(f, &env->mxccdata[i]);
> - }
> - for (i = 0; i < 8; i++) {
> - qemu_get_be64s(f, &env->mxccregs[i]);
> - }
> - qemu_get_be32s(f, &env->mmubpctrv);
> - qemu_get_be32s(f, &env->mmubpctrc);
> - qemu_get_be32s(f, &env->mmubpctrs);
> - qemu_get_be64s(f, &env->mmubpaction);
> - for (i = 0; i < 4; i++) {
> - qemu_get_be64s(f, &env->mmubpregs[i]);
> - }
> -#else
> - qemu_get_be64s(f, &env->lsu);
> - for (i = 0; i < 16; i++) {
> - qemu_get_be64s(f, &env->immuregs[i]);
> - qemu_get_be64s(f, &env->dmmuregs[i]);
> - }
> - for (i = 0; i < 64; i++) {
> - qemu_get_be64s(f, &env->itlb[i].tag);
> - qemu_get_be64s(f, &env->itlb[i].tte);
> - qemu_get_be64s(f, &env->dtlb[i].tag);
> - qemu_get_be64s(f, &env->dtlb[i].tte);
> - }
> - qemu_get_be32s(f, &env->mmu_version);
> - for (i = 0; i < MAXTL_MAX; i++) {
> - qemu_get_be64s(f, &env->ts[i].tpc);
> - qemu_get_be64s(f, &env->ts[i].tnpc);
> - qemu_get_be64s(f, &env->ts[i].tstate);
> - qemu_get_be32s(f, &env->ts[i].tt);
> - }
> - qemu_get_be32s(f, &env->xcc);
> - qemu_get_be32s(f, &env->asi);
> - qemu_get_be32s(f, &env->pstate);
> - qemu_get_be32s(f, &env->tl);
> - qemu_get_be32s(f, &env->cansave);
> - qemu_get_be32s(f, &env->canrestore);
> - qemu_get_be32s(f, &env->otherwin);
> - qemu_get_be32s(f, &env->wstate);
> - qemu_get_be32s(f, &env->cleanwin);
> - for (i = 0; i < 8; i++)
> - qemu_get_be64s(f, &env->agregs[i]);
> - for (i = 0; i < 8; i++)
> - qemu_get_be64s(f, &env->bgregs[i]);
> - for (i = 0; i < 8; i++)
> - qemu_get_be64s(f, &env->igregs[i]);
> - for (i = 0; i < 8; i++)
> - qemu_get_be64s(f, &env->mgregs[i]);
> - qemu_get_be64s(f, &env->fprs);
> - qemu_get_be64s(f, &env->tick_cmpr);
> - qemu_get_be64s(f, &env->stick_cmpr);
> - cpu_get_timer(f, env->tick);
> - cpu_get_timer(f, env->stick);
> - qemu_get_be64s(f, &env->gsr);
> - qemu_get_be32s(f, &env->gl);
> - qemu_get_be64s(f, &env->hpstate);
> - for (i = 0; i < MAXTL_MAX; i++)
> - qemu_get_be64s(f, &env->htstate[i]);
> - qemu_get_be64s(f, &env->hintp);
> - qemu_get_be64s(f, &env->htba);
> - qemu_get_be64s(f, &env->hver);
> - qemu_get_be64s(f, &env->hstick_cmpr);
> - qemu_get_be64s(f, &env->ssr);
> - cpu_get_timer(f, env->hstick);
> -#endif
> + cpu_put_psr(env, env->psr_vmstate);
This changes the behavior a bit: cpu_put_psr()->cpu_check_irqs() can
modify env->interrupt_index. I suspect the original behavior was unintended
though, doing this post-load seems to make a lot more sense.
> tlb_flush(env, 1);
> return 0;
> }
> +
> +const VMStateDescription vmstate_cpu = {
> + .name = "cpu",
> + .version_id = 7,
> + .minimum_version_id = 7,
> + .minimum_version_id_old = 7,
> + .pre_save = cpu_pre_save,
> + .post_load = cpu_post_load,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINTTL_ARRAY(gregs, CPUSPARCState, 8),
> + VMSTATE_UINT32(nwindows, CPUSPARCState),
> + VMSTATE_VARRAY_MULTIPLY(regbase, CPUSPARCState, nwindows, 16,
> + vmstate_info_uinttls, target_ulong),
> + VMSTATE_CPUDOUBLE_ARRAY(fpr, CPUSPARCState, TARGET_DPREGS),
> + VMSTATE_UINTTL(pc, CPUSPARCState),
> + VMSTATE_UINTTL(npc, CPUSPARCState),
> + VMSTATE_UINTTL(y, CPUSPARCState),
> + VMSTATE_UINT32(psr_vmstate, CPUSPARCState),
> + VMSTATE_UINTTL(fsr, CPUSPARCState),
> + VMSTATE_UINTTL(tbr, CPUSPARCState),
> + VMSTATE_INT32(interrupt_index, CPUSPARCState),
> + VMSTATE_UINT32(pil_in, CPUSPARCState),
> +#ifndef TARGET_SPARC64
> + /* MMU */
> + VMSTATE_UINT32(wim, CPUSPARCState),
> + VMSTATE_UINT32_ARRAY(mmuregs, CPUSPARCState, 32),
> + VMSTATE_UINT64_ARRAY(mxccdata, CPUSPARCState, 4),
> + VMSTATE_UINT64_ARRAY(mxccregs, CPUSPARCState, 8),
> + VMSTATE_UINT32(mmubpctrv, CPUSPARCState),
> + VMSTATE_UINT32(mmubpctrc, CPUSPARCState),
> + VMSTATE_UINT32(mmubpctrs, CPUSPARCState),
> + VMSTATE_UINT64(mmubpaction, CPUSPARCState),
> + VMSTATE_UINT64_ARRAY(mmubpregs, CPUSPARCState, 4),
> +#else
> + VMSTATE_UINT64(lsu, CPUSPARCState),
> + VMSTATE_UINT64(immuregs[0], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[0], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[1], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[1], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[2], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[2], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[3], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[3], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[4], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[4], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[5], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[5], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[6], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[6], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[7], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[7], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[8], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[8], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[9], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[9], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[10], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[10], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[11], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[11], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[12], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[12], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[13], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[13], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[14], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[14], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[15], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[15], CPUSPARCState),
> + VMSTATE_STRUCT(itlb[0], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[0], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[1], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[1], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[2], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[2], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[3], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[3], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[4], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[4], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[5], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[5], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[6], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[6], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[7], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[7], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[8], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[8], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[9], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[9], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[10], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[10], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[11], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[11], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[12], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[12], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[13], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[13], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[14], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[14], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[15], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[15], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[16], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[16], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[17], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[17], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[18], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[18], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[19], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[19], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[20], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[20], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[21], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[21], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[22], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[22], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[23], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[23], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[24], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[24], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[25], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[25], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[26], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[26], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[27], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[27], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[28], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[28], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[29], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[29], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[30], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[30], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[31], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[31], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[32], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[32], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[33], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[33], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[34], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[34], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[35], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[35], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[36], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[36], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[37], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[37], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[38], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[38], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[39], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[39], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[40], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[40], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[41], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[41], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[42], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[42], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[43], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[43], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[44], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[44], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[45], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[45], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[46], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[46], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[47], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[47], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[48], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[48], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[49], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[49], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[50], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[50], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[51], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[51], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[52], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[52], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[53], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[53], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[54], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[54], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[55], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[55], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[56], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[56], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[57], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[57], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[58], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[58], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[59], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[59], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[60], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[60], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[61], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[61], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[62], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[62], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[63], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[63], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_UINT32(mmu_version, CPUSPARCState),
> + VMSTATE_STRUCT_ARRAY(ts, CPUSPARCState, MAXTL_MAX, 0,
> + vmstate_trap_state, trap_state),
> + VMSTATE_UINT32(xcc, CPUSPARCState),
> + VMSTATE_UINT32(asi, CPUSPARCState),
> + VMSTATE_UINT32(pstate, CPUSPARCState),
> + VMSTATE_UINT32(tl, CPUSPARCState),
> + VMSTATE_UINT32(cansave, CPUSPARCState),
> + VMSTATE_UINT32(canrestore, CPUSPARCState),
> + VMSTATE_UINT32(otherwin, CPUSPARCState),
> + VMSTATE_UINT32(wstate, CPUSPARCState),
> + VMSTATE_UINT32(cleanwin, CPUSPARCState),
> + VMSTATE_UINT64_ARRAY(agregs, CPUSPARCState, 8),
> + VMSTATE_UINT64_ARRAY(bgregs, CPUSPARCState, 8),
> + VMSTATE_UINT64_ARRAY(igregs, CPUSPARCState, 8),
> + VMSTATE_UINT64_ARRAY(mgregs, CPUSPARCState, 8),
> + VMSTATE_UINT64(fprs, CPUSPARCState),
> + VMSTATE_UINT64(tick_cmpr, CPUSPARCState),
> + VMSTATE_UINT64(stick_cmpr, CPUSPARCState),
> + VMSTATE_CPU_TIMER(tick, CPUSPARCState),
> + VMSTATE_CPU_TIMER(stick, CPUSPARCState),
> + VMSTATE_UINT64(gsr, CPUSPARCState),
> + VMSTATE_UINT32(gl, CPUSPARCState),
> + VMSTATE_UINT64(hpstate, CPUSPARCState),
> + VMSTATE_UINT64_ARRAY(htstate, CPUSPARCState, MAXTL_MAX),
> + VMSTATE_UINT64(hintp, CPUSPARCState),
> + VMSTATE_UINT64(htba, CPUSPARCState),
> + VMSTATE_UINT64(hver, CPUSPARCState),
> + VMSTATE_UINT64(hstick_cmpr, CPUSPARCState),
> + VMSTATE_UINT64(ssr, CPUSPARCState),
> + VMSTATE_CPU_TIMER(hstick, CPUSPARCState),
> +#endif
> + VMSTATE_END_OF_LIST()
> + },
> +};
> --
> 1.7.7.6
>
>
next prev parent reply other threads:[~2012-03-21 22:46 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 01/36] vmstate: Simplify test for CPU_SAVE_VERSION Juan Quintela
2012-03-21 20:35 ` Michael Roth
2012-03-19 22:57 ` [Qemu-devel] [PATCH 02/36] vmstate: make all architectures export a way to migrate cpu's Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 03/36] vmstate: unicore32 don't support cpu migration Juan Quintela
2012-03-21 20:49 ` Michael Roth
2012-03-19 22:57 ` [Qemu-devel] [PATCH 04/36] vmstate: use new cpu style for x86 Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 05/36] vmstate: use new style for lm32 cpus Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 06/36] vmstate: make microblaze cpus not migrateable Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 07/36] vmstate: port cris cpu to vmstate Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 08/36] vmstate: machine.c is only compiled for !CONFIG_USER_ONLY Juan Quintela
2012-03-21 18:09 ` Andreas Färber
2012-03-21 19:20 ` Peter Maydell
2012-03-19 22:57 ` [Qemu-devel] [PATCH 09/36] vmstate: introduce float32 arrays Juan Quintela
2012-03-20 14:11 ` Peter Maydell
2012-03-20 15:20 ` Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 10/36] vmstate: introduce float64 arrays Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 11/36] vmstate: introduce CPU_DoubleU arrays Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 12/36] vmstate: Introduce VMSTATE_STRUCT_VARRAY_INT32_TEST Juan Quintela
2012-03-21 20:16 ` Igor Mitsyanko
2012-03-19 22:57 ` [Qemu-devel] [PATCH 13/36] vmstate: port ppc cpu Juan Quintela
2012-03-21 21:52 ` Michael Roth
2012-03-21 21:56 ` Peter Maydell
2012-03-19 22:57 ` [Qemu-devel] [PATCH 14/36] vmstate: introduce VMSTATE_VARRAY_MULTIPLY Juan Quintela
2012-03-21 20:54 ` Igor Mitsyanko
2012-03-19 22:57 ` [Qemu-devel] [PATCH 15/36] vmstate: define vmstate_info_uinttls Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 16/36] vmstate: port sparc cpu Juan Quintela
2012-03-21 22:46 ` Michael Roth [this message]
2012-03-24 12:32 ` Blue Swirl
2012-03-19 22:57 ` [Qemu-devel] [PATCH 17/36] vmstate: make incompatible change for sparc Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 18/36] mips_fulong2e: cpu vmstate already registered in cpu_exec_init Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 19/36] mips: make mvp an embedded struct instead of a pointer Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 20/36] mips: make tlb " Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 21/36] mips: bump migration version to 4 Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 22/36] vmstate: port mips cpu Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 23/36] arm: save always 32 fpu registers Juan Quintela
2012-03-20 11:54 ` Peter Maydell
2012-03-20 12:27 ` Juan Quintela
2012-03-20 13:48 ` Peter Maydell
2012-03-19 22:57 ` [Qemu-devel] [PATCH 24/36] vmstate: port arm cpu Juan Quintela
2012-03-21 16:29 ` Andreas Färber
2012-03-21 16:42 ` Peter Maydell
2012-03-21 17:16 ` Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 25/36] vmstate: all cpus converted Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 26/36] vmstate: fix vmstate formating for i386 Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 27/36] vmstate: remove unneeded includes from target-*/machine.c Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 28/36] vmstate: rename machine.c to vmstate-cpu.c Juan Quintela
2012-03-22 12:42 ` Andreas Färber
2012-03-22 13:13 ` Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 29/36] vmstate: Add copyright info for alpha processor Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 30/36] vmstate: Add copyright info for lm32 processor Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 31/36] vmstate: Add copyright info for cris processor Juan Quintela
2012-03-19 22:58 ` [Qemu-devel] [PATCH 32/36] vmstate: Add copyright info for arm processor Juan Quintela
2012-03-19 22:58 ` [Qemu-devel] [PATCH 33/36] vmstate: Add copyright info for i386 processor Juan Quintela
2012-03-19 22:58 ` [Qemu-devel] [PATCH 34/36] vmstate: Add copyright info for mips processor Juan Quintela
2012-03-19 22:58 ` [Qemu-devel] [PATCH 35/36] vmstate: Add copyright info for ppc processor Juan Quintela
2012-03-19 22:58 ` [Qemu-devel] [PATCH 36/36] vmstate: Add copyright info for sparc processor Juan Quintela
2012-03-21 17:13 ` [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Andreas Färber
2012-03-21 17:24 ` Juan Quintela
2012-03-21 18:43 ` Andreas Färber
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