From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 03/37] drm/i915: add HAS_PLL_SPLIT macro Date: Thu, 22 Mar 2012 11:06:41 +0100 Message-ID: <20120322100641.GD6195@phenom.ffwll.local> References: <1332378612-3814-1-git-send-email-eugeni.dodonov@intel.com> <1332378612-3814-4-git-send-email-eugeni.dodonov@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-wi0-f171.google.com (mail-wi0-f171.google.com [209.85.212.171]) by gabe.freedesktop.org (Postfix) with ESMTP id 3DC35A09D8 for ; Thu, 22 Mar 2012 03:05:58 -0700 (PDT) Received: by wibhj13 with SMTP id hj13so350904wib.12 for ; Thu, 22 Mar 2012 03:05:57 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1332378612-3814-4-git-send-email-eugeni.dodonov@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Eugeni Dodonov Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Mar 21, 2012 at 10:09:38PM -0300, Eugeni Dodonov wrote: > Ivy Bridge is the only GPU which has split 3-display support over 2 PLLs. > > Signed-off-by: Eugeni Dodonov This is imo a strange name for '3 pipes but just 2 plls' hw. And I couldn't find any usage of this in your series, so I don't know how you intend to use it. But usually for such narrow, single-chip special cases I prefer a fe IS_IVB checks in the code instead of this indirection. -Daniel > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 49488e1..fb50c42 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1048,6 +1048,7 @@ struct drm_i915_file_private { > #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) > > #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) > +#define HAS_PLL_SPLIT(dev) (IS_IVYBRIDGE(dev)) > #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) > > #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) > -- > 1.7.9.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48