From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Subject: Re: [PATCH 11/22] drm/i915: Enable DP panel power
 sequencing for ValleyView
Date: Wed, 28 Mar 2012 16:57:12 -0700
Message-ID: <20120328165712.204bbe98@jbarnes-desktop>
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To: Daniel Vetter <daniel@ffwll.ch>
Cc: Beeresh G <beeresh.g@intel.com>, intel-gfx@lists.freedesktop.org
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On Wed, 28 Mar 2012 23:59:33 +0200
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Wed, Mar 28, 2012 at 01:39:31PM -0700, Jesse Barnes wrote:
> > From: Shobhit Kumar <shobhit.kumar@intel.com>
> > 
> > VLV supports two dp panels, there are two set of panel power sequence
> > registers which needed to be programmed based on the configured
> > pipe. This patch add supports for the same
> > 
> > Acked-by: Acked-by: Ben Widawsky <ben@bwidawsk.net>
> > Signed-off-by: Beeresh G <beeresh.g@intel.com>
> > Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> > Reviewed-by: Jesse Barnes <jesse.barnes@intel.com>
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> 
> Afaics we use these PP_ regs at tons of other places. Do we not need them
> there or will that follow in a later patch?
> -Daniel

Later patch; this one hasn't been tested yet either.

-- 
Jesse Barnes, Intel Open Source Technology Center