From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 2/7 v6] drm/i915/intel_i2c: use double-buffered writes Date: Thu, 29 Mar 2012 11:15:47 +0200 Message-ID: <20120329091547.GE4106@phenom.ffwll.local> References: <1332959199-32161-1-git-send-email-djkurtz@chromium.org> <1332959199-32161-3-git-send-email-djkurtz@chromium.org> <1332960093_131068@CP5-2952> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Daniel Kurtz Cc: Chris Wilson , Daniel Vetter , Keith Packard , David Airlie , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Benson Leung , Yufeng Shen List-Id: dri-devel@lists.freedesktop.org On Thu, Mar 29, 2012 at 04:46:39PM +0800, Daniel Kurtz wrote: > On Thu, Mar 29, 2012 at 2:41 AM, Chris Wilson wrote: > > On Thu, 29 Mar 2012 02:26:34 +0800, Daniel Kurtz wrote: > >> The GMBUS controller GMBUS3 register is double-buffered. =A0Take a= dvantage > >> of this =A0by writing two 4-byte words before the first wait for H= W_RDY. > >> This helps keep the GMBUS controller from becoming idle during lon= g writes. > >> > >> Signed-off-by: Daniel Kurtz > > > > "For byte counts that are greater than four bytes, this register wi= ll be > > written with subsequent data only after the HW_RDY status bit is se= t" > > > > Hmm, I had interpretted that as should only be. But if you take int= o > > account that the register is indeed double-buffered, it does make s= ense > > that the hardware itself is only updated after the HW_RDY signal. > > Reviewed-by: Chris Wilson >=20 > In fact, during my experiments using the GMBUS interrupts, the HW_RDY > interrupt would only trigger for transactions > 4 bytes after 2 write= s > to GMBUS3. I think that's rather important information. Can you add this to your commit message? -Daniel --=20 Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48