From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 5/7 v6] drm/i915/intel_i2c: use INDEX cycles for i2c read transactions Date: Thu, 29 Mar 2012 11:25:32 +0200 Message-ID: <20120329092532.GF4106@phenom.ffwll.local> References: <1332959199-32161-1-git-send-email-djkurtz@chromium.org> <1332959199-32161-6-git-send-email-djkurtz@chromium.org> <1332960747_131180@CP5-2952> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Daniel Kurtz Cc: Chris Wilson , Daniel Vetter , Keith Packard , David Airlie , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Benson Leung , Yufeng Shen List-Id: dri-devel@lists.freedesktop.org On Thu, Mar 29, 2012 at 04:37:18PM +0800, Daniel Kurtz wrote: > On Thu, Mar 29, 2012 at 2:52 AM, Chris Wilson wrote: > > On Thu, 29 Mar 2012 02:26:37 +0800, Daniel Kurtz wrote: > >> It is very common for an i2c device to require a small 1 or 2 byte= write > >> followed by a read. =A0For example, when reading from an i2c EEPRO= M it is > >> common to write and address, offset or index followed by a reading= some > >> values. > > > > Hmm, I have > > > > "gmbus1, bits 8-15: 8-bit GMBUS slave register > > This field is redundant and should not be used." > > > > Scary. :) >=20 > Perhaps INDEX ops are only available on some chipsets? > Is this something you can double check? I think index ops are available, the text sounds more like a hint to th= e programmer that for VCH devices you should use word reg index access (i= =2Ee. gmbus 5). We'll see when it blows up. -Daniel --=20 Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48