From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mike Frysinger Date: Wed, 25 Apr 2012 18:54:40 -0400 Subject: [U-Boot] [PATCH 2/2] mmc: tegra: invalidate complete cachelines In-Reply-To: <1335254024-30115-2-git-send-email-thierry.reding@avionic-design.de> References: <1335254024-30115-1-git-send-email-thierry.reding@avionic-design.de> <1335254024-30115-2-git-send-email-thierry.reding@avionic-design.de> Message-ID: <201204251854.41947.vapier@gentoo.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Tuesday 24 April 2012 03:53:44 Thierry Reding wrote: > The MMC core sometimes reads buffers that are smaller than a complete > cacheline, for example when reading the SCR. In order to avoid a warning > from the ARM v7 cache handling code, this patch makes sure that complete > cachelines are flushed. this is still wrong. all you've done is bypass the error message without addressing the underlying problem -- you're invalidating too much. -mike -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 836 bytes Desc: This is a digitally signed message part. URL: