From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1946819Ab2ERXHr (ORCPT ); Fri, 18 May 2012 19:07:47 -0400 Received: from mail-pb0-f46.google.com ([209.85.160.46]:53524 "EHLO mail-pb0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1946802Ab2ERXHk (ORCPT ); Fri, 18 May 2012 19:07:40 -0400 Message-Id: <20120518212653.182566715@linuxfoundation.org> User-Agent: quilt/0.60-19.1 Date: Fri, 18 May 2012 14:27:33 -0700 From: Greg KH To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: torvalds@linux-foundation.org, akpm@linux-foundation.org, alan@lxorguk.ukuu.org.uk, Tomoya MORINAGA , Grant Likely Subject: [ 44/47] spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control In-Reply-To: <20120518212701.GA5023@kroah.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 3.3-stable review patch. If anyone has any objections, please let me know. ------------------ From: Tomoya MORINAGA commit f258b44e22e07f5e98ac2260c70acff5784791b6 upstream. This patch supports a spi mode setup and bit order setup by IO control. spi mode: mode 0 to mode 3 bit order: LSB first, MSB first Signed-off-by: Tomoya MORINAGA Signed-off-by: Grant Likely Signed-off-by: Greg Kroah-Hartman --- drivers/spi/spi-topcliff-pch.c | 1 + 1 file changed, 1 insertion(+) --- a/drivers/spi/spi-topcliff-pch.c +++ b/drivers/spi/spi-topcliff-pch.c @@ -1434,6 +1434,7 @@ static int __devinit pch_spi_pd_probe(st master->num_chipselect = PCH_MAX_CS; master->setup = pch_spi_setup; master->transfer = pch_spi_transfer; + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; data->board_dat = board_dat; data->plat_dev = plat_dev;