From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:51084) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SVfYp-0001TB-0q for qemu-devel@nongnu.org; Sat, 19 May 2012 05:02:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SVfYn-0006pz-8h for qemu-devel@nongnu.org; Sat, 19 May 2012 05:02:50 -0400 Received: from hall.aurel32.net ([88.191.126.93]:44681) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SVfYn-0006p6-2S for qemu-devel@nongnu.org; Sat, 19 May 2012 05:02:49 -0400 Date: Sat, 19 May 2012 11:02:40 +0200 From: Aurelien Jarno Message-ID: <20120519090239.GA15511@hall.aurel32.net> References: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: Sender: Aurelien Jarno Subject: Re: [Qemu-devel] r4k doesn't support movz List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Zhi-zhou Zhang Cc: qemu-devel@nongnu.org On Fri, May 18, 2012 at 07:38:39PM +0800, Zhi-zhou Zhang wrote: > Hi Aurelien, > > I found that when qemu-system-mips64el executed 'movz' with -M mips, it > would raise a reserved instruction exception. > The mips spec describes movz as below: > > Mnemonic Instructio Defined in MIPS ISA > MOVZ Move Conditional on Zero MIPS32 > > I think ISA-64 should support MIPS32 instructions for compatible. am I > right? > MIPS64 does support MIPS32 instructions. That said, the default CPU of the mips machine with qemu-system-mips64el is an R4000 CPU which doesn't support this instruction. You should try for example with a 5Kc, 5Kf or 20Kc CPU. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net