From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:57627) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Se5lC-0004vD-Ti for qemu-devel@nongnu.org; Mon, 11 Jun 2012 10:38:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Se5l1-0005NQ-Pe for qemu-devel@nongnu.org; Mon, 11 Jun 2012 10:38:26 -0400 Received: from mail-lpp01m010-f45.google.com ([209.85.215.45]:52148) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Se5l1-0005Mk-43 for qemu-devel@nongnu.org; Mon, 11 Jun 2012 10:38:15 -0400 Received: by lahc1 with SMTP id c1so3131495lah.4 for ; Mon, 11 Jun 2012 07:38:11 -0700 (PDT) Date: Mon, 11 Jun 2012 16:38:04 +0200 From: "Edgar E. Iglesias" Message-ID: <20120611143803.GA29685@edde.se.axis.com> References: <4FD208F6.3020307@codemonkey.ws> <4FD5EF75.7060707@us.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Subject: Re: [Qemu-devel] [RFC] QOMification of AXI stream List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Anthony Liguori , Michal Simek , "qemu-devel@nongnu.org Developers" , Peter Crosthwaite , Paul Brook , Anthony Liguori , Andreas =?iso-8859-1?Q?F=E4rber?= , John Williams On Mon, Jun 11, 2012 at 02:39:56PM +0100, Peter Maydell wrote: > On 11 June 2012 14:15, Anthony Liguori wrote: > > From what you said earlier, it's basically: > > > > 'write data to this address' > > 'read data from this address' > > > > An interface that implements this is DMAContext.  Forget about the fact that > > 'DMA' is in the name.  It's really the symmetric version of a MemoryRegion. > > ...so can we fix the name? > > Ideally the interface used by DMA controllers should be identical to > the interface used by CPUs to talk to the rest of the system: it's > exactly the same bus interface in hardware, after all. I thought we were talking about the interface between the DMA ctrl and the I/O (devices). Not between the DMA and the "memory" bus system. Cheers