From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:40062) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Se64d-0002Yo-6h for qemu-devel@nongnu.org; Mon, 11 Jun 2012 10:58:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Se64W-000224-P0 for qemu-devel@nongnu.org; Mon, 11 Jun 2012 10:58:30 -0400 Received: from mail-lb0-f173.google.com ([209.85.217.173]:38031) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Se64W-00021L-9p for qemu-devel@nongnu.org; Mon, 11 Jun 2012 10:58:24 -0400 Received: by lbok6 with SMTP id k6so3291061lbo.4 for ; Mon, 11 Jun 2012 07:58:21 -0700 (PDT) Date: Mon, 11 Jun 2012 16:58:17 +0200 From: "Edgar E. Iglesias" Message-ID: <20120611145817.GB29685@edde.se.axis.com> References: <4FD208F6.3020307@codemonkey.ws> <4FD5EF75.7060707@us.ibm.com> <20120611143803.GA29685@edde.se.axis.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [RFC] QOMification of AXI stream List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Anthony Liguori , Michal Simek , "qemu-devel@nongnu.org Developers" , Peter Crosthwaite , Paul Brook , Anthony Liguori , Andreas =?iso-8859-1?Q?F=E4rber?= , John Williams On Mon, Jun 11, 2012 at 03:53:23PM +0100, Peter Maydell wrote: > On 11 June 2012 15:38, Edgar E. Iglesias wrote: > > On Mon, Jun 11, 2012 at 02:39:56PM +0100, Peter Maydell wrote: > >> Ideally the interface used by DMA controllers should be identical to > >> the interface used by CPUs to talk to the rest of the system: it's > >> exactly the same bus interface in hardware, after all. > > > > I thought we were talking about the interface between the DMA ctrl > > and the I/O (devices). Not between the DMA and the "memory" bus system. > > In hardware (at least for AXI) they're the same thing. A DMA > controller is a bus master, just like a CPU. They don't care > whether the slave is RAM or a device, they're just issuing > memory transactions to addresses. In many cases they are not the same thing. The DMA controller has an interface to the bus (the one you refer to) and in many cases dedicated channels connected to the various devices. These channels may or may not resemble the bus a CPU uses, typically they don't. There are of course systems of any kind, even ones that use the system bus to transfer data from the DMA to/from the devices.