From: Daniel Vetter <daniel@ffwll.ch>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/7] drm/i915: add HDMI and DP port enumeration on ValleyView
Date: Wed, 13 Jun 2012 10:11:09 +0200 [thread overview]
Message-ID: <20120613081109.GC4829@phenom.ffwll.local> (raw)
In-Reply-To: <1339537655-5792-5-git-send-email-jbarnes@virtuousgeek.org>
On Tue, Jun 12, 2012 at 02:47:32PM -0700, Jesse Barnes wrote:
> ValleyView is similar to IbexPeak here, but with different register
> offsets.
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
> drivers/gpu/drm/i915/intel_display.c | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 5006928..2a677f8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6772,7 +6772,24 @@ static void intel_setup_outputs(struct drm_device *dev)
>
> if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
> intel_dp_init(dev, PCH_DP_D);
> + } else if (IS_VALLEYVIEW(dev)) {
> + int found;
> +
> + if (I915_READ(VLV_HDMIB) & PORT_DETECTED) {
VLV_HDMIB == SDVOB, which royally confused me, especially since below you
use SDVOC for VLV_HDMC. Yeah, pre-pch_split we just use the SDVO names for
the HDMI registers. I guess I'll just wait for Paulo to clean up this
mess.
> + /* SDVOB multiplex with HDMIB */
> + found = intel_sdvo_init(dev, VLV_HDMIB, true);
> + if (!found)
> + intel_hdmi_init(dev, VLV_HDMIB);
> + if (!found && (I915_READ(DP_B) & DP_DETECTED))
> + intel_dp_init(dev, DP_B);
> + }
> +
> + if (I915_READ(SDVOC) & PORT_DETECTED)
> + intel_hdmi_init(dev, SDVOC);
>
> + /* Shares lanes with HDMI on SDVOC */
> + if (!dpd_is_edp && (I915_READ(DP_C) & DP_DETECTED))
> + intel_dp_init(dev, DP_C);
This !dpd_is_edp check here looks fishy for DP_C, copy&paste fail?
Also, I wonder where you set up the vlv eDP panels?
> } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
> bool found = false;
>
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
next prev parent reply other threads:[~2012-06-13 8:09 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-06-12 21:47 Remaining VLV patches Jesse Barnes
2012-06-12 21:47 ` [PATCH 1/7] drm/i915: ValleyView mode setting limits and PLL functions Jesse Barnes
2012-06-13 8:06 ` Daniel Vetter
2012-06-13 15:04 ` Purushothaman, Vijay A
2012-06-12 21:47 ` [PATCH 2/7] drm/i915: Enable DP panel power sequencing for ValleyView Jesse Barnes
2012-06-13 8:05 ` Daniel Vetter
2012-06-13 16:10 ` Shobhit Kumar
2012-06-12 21:47 ` [PATCH 3/7] drm/i915: add ValleyView specific CRT detect function Jesse Barnes
2012-06-12 21:47 ` [PATCH 4/7] drm/i915: add HDMI and DP port enumeration on ValleyView Jesse Barnes
2012-06-13 8:11 ` Daniel Vetter [this message]
2012-06-13 17:19 ` Jesse Barnes
2012-06-12 21:47 ` [PATCH 5/7] drm/i915: access VLV regs through read/write switch Jesse Barnes
2012-06-13 8:14 ` Daniel Vetter
2012-06-12 21:47 ` [PATCH 6/7] drm/i915: bind driver to ValleyView chipsets Jesse Barnes
2012-06-12 21:47 ` [PATCH 7/7] drm/i915: VLV VGA port only handles on & off, like PCH VGA Jesse Barnes
2012-06-13 8:36 ` Daniel Vetter
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