From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:39644) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Sezqs-0003t0-KT for qemu-devel@nongnu.org; Wed, 13 Jun 2012 22:32:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Sezqq-0004kp-NM for qemu-devel@nongnu.org; Wed, 13 Jun 2012 22:32:02 -0400 Received: from mail-bk0-f45.google.com ([209.85.214.45]:42300) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Sezqq-0004j6-DX for qemu-devel@nongnu.org; Wed, 13 Jun 2012 22:32:00 -0400 Received: by mail-bk0-f45.google.com with SMTP id j10so1088815bkw.4 for ; Wed, 13 Jun 2012 19:31:59 -0700 (PDT) Date: Thu, 14 Jun 2012 04:31:54 +0200 From: "Edgar E. Iglesias" Message-ID: <20120614023154.GB29384@zapo> References: <4FD62B5C.4040106@redhat.com> <4FD63A7F.8090902@codemonkey.ws> <1339452058.9220.32.camel@pasglop> <4FD67132.1060001@codemonkey.ws> <4FD7100F.3080207@redhat.com> <1339547861.9220.77.camel@pasglop> <20120614000001.GA26263@zapo> <1339637650.9220.134.camel@pasglop> <20120614020306.GA29384@zapo> <1339640205.9220.139.camel@pasglop> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1339640205.9220.139.camel@pasglop> Subject: Re: [Qemu-devel] [RFC] QOMification of AXI streams List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Benjamin Herrenschmidt Cc: Peter Maydell , Anthony Liguori , "qemu-devel@nongnu.org Developers" , Peter Crosthwaite , Michal Simek , Avi Kivity , Anthony Liguori , Andreas =?iso-8859-1?Q?F=E4rber?= , John Williams , Paul Brook On Thu, Jun 14, 2012 at 12:16:45PM +1000, Benjamin Herrenschmidt wrote: > On Thu, 2012-06-14 at 04:03 +0200, Edgar E. Iglesias wrote: > > Thanks for the clarificatino Ben. > > > > I don't know much about PCI but in the embedded world I've never seen > > anything that resemblems what you describe. Devices at the bottom of > > the hierharcy (or at any location) that make acceses to the memory system > > do it through a different port located at a differnt logical position in > > the hierarchy. > > Right, that's what I meant when I said that master and slave interfaces > don't have to be the same, but that's not a problem. A given device > could depend on two memory regions, one for downstream accesses only and > one for upstream accesses, both located in different positions in the > hierarchy. > > > In fact, a DMA ctrl can through it's master port access it's > > slave port without it even noticing that it is the same device accessing > > itself and the access will travel top-down through the bus hierarchy. > > That sometimes work ... and sometimes doesn't ... some combinations of > busses/devices will not allow that, some will deadlock, it really > depends on the setup. > > > I've never seen address decoding beeing done in reverse.. bottom-up. > > It really depends on the bus type and happens on embedded as well. > > If your device master "port" is directly on the processor bus, you still > have to deal with sibling devices potentially decoding right ? Now, what > about you have a bridge from that bus to another bus. For example ppc > PLB to AXI (that stuff exist out on the field). > > An AXI device might issue a cycle on the AXI portion, that can be > decoded by either a sibling AXI device ... or go up. In most cases No, it doesn't really go up.. This is where we disagree. > though, "upstream" is some kind of substractive decoding (ie. anything > -not- decoded by a sibling goes up). I've never seen this happen, but I won't say it doesn't exist because you'll find all kinds of HW out there that'll do all kind of stuff you wouldn't imagine. > > This gets even more obvious with PCI of course. Then add a b43 wifi card > on PCI, you have AXI -> PCI -> SSB (silicon backplane). Now what happens > when one of the sub-devices on SBB (the MAC interface for example) does > a bus master ? You have at least 2 layers to cross before you hit your > processor bus. > > Add iommu's to the soup and you get into a serious mess :-) IOmmus messify things a bit, but the translation is only done from the masters above the iommu going down theough the iommu. Not vice versa. At least AFAIK. Cheers