From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 2/2] drm/i915: adjust framebuffer base
 address on gen4+
Date: Thu, 5 Jul 2012 13:38:55 +0200
Message-ID: <20120705113855.GI5203@phenom.ffwll.local>
References: <1341483450-6385-1-git-send-email-daniel.vetter@ffwll.ch>
	<1341483450-6385-2-git-send-email-daniel.vetter@ffwll.ch>
	<1341484214_176904@CP5-2952>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org>
Received: from mail-we0-f177.google.com (mail-we0-f177.google.com
	[74.125.82.177])
	by gabe.freedesktop.org (Postfix) with ESMTP id E150AA0E4A
	for <intel-gfx@lists.freedesktop.org>;
	Thu,  5 Jul 2012 04:38:59 -0700 (PDT)
Received: by werb13 with SMTP id b13so3306350wer.36
	for <intel-gfx@lists.freedesktop.org>;
	Thu, 05 Jul 2012 04:38:59 -0700 (PDT)
Content-Disposition: inline
In-Reply-To: <1341484214_176904@CP5-2952>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>, Intel Graphics Development <intel-gfx@lists.freedesktop.org>
List-Id: intel-gfx@lists.freedesktop.org

On Thu, Jul 05, 2012 at 11:29:10AM +0100, Chris Wilson wrote:
> On Thu,  5 Jul 2012 12:17:30 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> > The tileoffset register only supports a limited offset in x/y of 4096,
> > so for giant screen configuration with a shared fb we wrap around.
> > 
> > Fix this by computing a linear offset in tiles (pages) and only use
> > the tileoffset register to offset within the tile.
> > 
> > Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> Both Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Thanks for the review, I've addressed your pitch concern from the other
mail by merging one of Ville's patches.

> We could do with validating that the CRTC is within the fb->obj,
> otherwise we run foul of hanging the hardware. (Since this is a
> pre-existing condition it doesn't mar these patches.)
> 
> So the only question is whether we indicate to userspace that the kernel
> is fixed? Or just kill the w/a in userspace and for reasons of sanity
> strongly encourage everyone who hits this to upgrade? Since this is no
> stable material, having keeping the w/a seems to make sense...

As discussed I think we'll just ask ppl to upgrade their kernel and should
rip out the hack in userspace ...
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48