diff for duplicates of <201207062008.23952.arnd@arndb.de> diff --git a/a/1.txt b/N1/1.txt index aa0ece4..779369f 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -49,7 +49,7 @@ when it's called with a specific argument. If you want to keep that behavior, this handler cannot be generic across all mvebu socs, whereas registering four chained handlers for the same primary interrupt would have -the same effect at a very small runtime overhead without the +the same effect@a very small runtime overhead without the need for any special case. Arnd diff --git a/a/content_digest b/N1/content_digest index b3820d2..0cde99b 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,20 +1,10 @@ "ref\01341325365-21393-1-git-send-email-andrew@lunn.ch\0" "ref\0201207051454.24475.arnd@arndb.de\0" "ref\020120705161600.GA28860@lunn.ch\0" - "ref\020120705161600.GA28860-g2DYL2Zd6BY@public.gmane.org\0" - "From\0Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>\0" - "Subject\0Re: [PATCH v2 01/12] ARM: Orion: DT support for IRQ and GPIO Controllers\0" + "From\0arnd@arndb.de (Arnd Bergmann)\0" + "Subject\0[PATCH v2 01/12] ARM: Orion: DT support for IRQ and GPIO Controllers\0" "Date\0Fri, 6 Jul 2012 20:08:23 +0000\0" - "To\0Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>\0" - "Cc\0Sebastian Hesselbarth <sebastian.hesselbarth-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>" - linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org - Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org> - devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org - rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org - grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org - Michael Walle <michael-QKn5cuLxLXY@public.gmane.org> - linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - " spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Thursday 05 July 2012, Andrew Lunn wrote:\n" @@ -68,9 +58,9 @@ "If you want to keep that behavior, this handler cannot be\n" "generic across all mvebu socs, whereas registering four\n" "chained handlers for the same primary interrupt would have\n" - "the same effect at a very small runtime overhead without the\n" + "the same effect@a very small runtime overhead without the\n" "need for any special case.\n" "\n" "\tArnd" -1aa041d41f920575abba306d2b0697f92e4716d2d821f91ce6cef2f24a55f486 +06ca87cc9e767b1dc44d04c37b596d00f1dde54306d19066a4feb853b7f81d4e
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